From d140fa14f4c82139bfaae5ce0b2f3ff51db7a8cf Mon Sep 17 00:00:00 2001 From: Radvall Date: Fri, 31 Mar 2023 21:47:58 +0300 Subject: [PATCH 1/7] Add spice entry for JK Flip Flop --- qucs/components/jkff_SR.cpp | 22 ++++++++++++++++++++++ qucs/components/jkff_SR.h | 1 + qucs/module.cpp | 2 +- 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/qucs/components/jkff_SR.cpp b/qucs/components/jkff_SR.cpp index d8817e7f8..1515a5e0d 100644 --- a/qucs/components/jkff_SR.cpp +++ b/qucs/components/jkff_SR.cpp @@ -18,6 +18,7 @@ #include "jkff_SR.h" #include "node.h" #include "misc.h" +#include "extsimkernels/spicecompat.h" jkff_SR::jkff_SR() { @@ -37,6 +38,7 @@ jkff_SR::jkff_SR() ty = y2 + 4; Model = "jkff_SR"; Name = "Y"; + SpiceModel = "A"; } Component * jkff_SR::newOne() @@ -183,3 +185,23 @@ QString jkff_SR::verilogCode( int ) " end\n"; return l; } + +QString jkff_SR::spice_netlist(bool isXyce) +{ + if (isXyce) return QString(""); + + QString s = SpiceModel + Name; + QString tmp_model = "model_" + Name; + QString td = spicecompat::normalize_value(getProperty("Delay")->Value); + s += " " + Ports.at(1)->Connection->Name; + s += " " + Ports.at(3)->Connection->Name; + s += " " + Ports.at(2)->Connection->Name; + s += " " + Ports.at(0)->Connection->Name; + s += " " + Ports.at(4)->Connection->Name; + s += " " + Ports.at(6)->Connection->Name; + s += " " + Ports.at(5)->Connection->Name; + s += " " + tmp_model + "\n"; + s += QString(".model %1 d_jkff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n") + .arg(tmp_model).arg(td); + return s; +} diff --git a/qucs/components/jkff_SR.h b/qucs/components/jkff_SR.h index 094e37f54..8a06993b3 100644 --- a/qucs/components/jkff_SR.h +++ b/qucs/components/jkff_SR.h @@ -24,6 +24,7 @@ class jkff_SR : public Component void createSymbol(); QString vhdlCode(int); QString verilogCode(int); + QString spice_netlist(bool isXyce); }; #endif /* jkff_SR_H */ diff --git a/qucs/module.cpp b/qucs/module.cpp index b43f6e5c2..a26cdb811 100644 --- a/qucs/module.cpp +++ b/qucs/module.cpp @@ -451,7 +451,6 @@ void Module::registerModules (void) { REGISTER_DIGITAL_1 (D_FlipFlop); REGISTER_DIGITAL_1 (dff_SR); REGISTER_DIGITAL_1 (JK_FlipFlop); - REGISTER_DIGITAL_1 (jkff_SR); REGISTER_DIGITAL_1 (tff_SR); REGISTER_DIGITAL_1 (gatedDlatch); REGISTER_DIGITAL_1 (logic_0); @@ -482,6 +481,7 @@ void Module::registerModules (void) { REGISTER_DIGITAL_1 (Logical_AND); REGISTER_DIGITAL_1 (Logical_XOR); REGISTER_DIGITAL_1 (Logical_XNOR); + REGISTER_DIGITAL_1 (jkff_SR); } // file components From e5b6b4df203e4ffe4d9b150faefbb285e5ae5c59 Mon Sep 17 00:00:00 2001 From: Radvall Date: Fri, 31 Mar 2023 22:00:25 +0300 Subject: [PATCH 2/7] Add spice entry for D Flip Flop --- qucs/components/dff_SR.cpp | 21 +++++++++++++++++++++ qucs/components/dff_SR.h | 1 + qucs/module.cpp | 2 +- 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/qucs/components/dff_SR.cpp b/qucs/components/dff_SR.cpp index 8c823f838..e5f9ea8e3 100644 --- a/qucs/components/dff_SR.cpp +++ b/qucs/components/dff_SR.cpp @@ -18,6 +18,7 @@ #include "dff_SR.h" #include "node.h" #include "misc.h" +#include "extsimkernels/spicecompat.h" dff_SR::dff_SR() { @@ -37,6 +38,7 @@ dff_SR::dff_SR() ty = y2 + 4; Model = "dff_SR"; Name = "Y"; + SpiceModel = "A"; } Component * dff_SR::newOne() @@ -173,3 +175,22 @@ QString dff_SR::verilogCode( int ) " end\n"; return l; } + +QString dff_SR::spice_netlist(bool isXyce) +{ + if (isXyce) return QString(""); + + QString s = SpiceModel + Name; + QString tmp_model = "model_" + Name; + QString td = spicecompat::normalize_value(getProperty("Delay")->Value); + s += " " + Ports.at(1)->Connection->Name; + s += " " + Ports.at(2)->Connection->Name; + s += " " + Ports.at(0)->Connection->Name; + s += " " + Ports.at(3)->Connection->Name; + s += " " + Ports.at(5)->Connection->Name; + s += " " + Ports.at(4)->Connection->Name; + s += " " + tmp_model + "\n"; + s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n") + .arg(tmp_model).arg(td); + return s; +} diff --git a/qucs/components/dff_SR.h b/qucs/components/dff_SR.h index 2d6adcad2..72ae7c113 100644 --- a/qucs/components/dff_SR.h +++ b/qucs/components/dff_SR.h @@ -24,6 +24,7 @@ class dff_SR : public Component void createSymbol(); QString vhdlCode(int); QString verilogCode(int); + QString spice_netlist(bool isXyce); }; #endif /* dff_SR_H */ diff --git a/qucs/module.cpp b/qucs/module.cpp index a26cdb811..95896ac82 100644 --- a/qucs/module.cpp +++ b/qucs/module.cpp @@ -449,7 +449,6 @@ void Module::registerModules (void) { REGISTER_DIGITAL_1 (fa2b); REGISTER_DIGITAL_1 (RS_FlipFlop); REGISTER_DIGITAL_1 (D_FlipFlop); - REGISTER_DIGITAL_1 (dff_SR); REGISTER_DIGITAL_1 (JK_FlipFlop); REGISTER_DIGITAL_1 (tff_SR); REGISTER_DIGITAL_1 (gatedDlatch); @@ -481,6 +480,7 @@ void Module::registerModules (void) { REGISTER_DIGITAL_1 (Logical_AND); REGISTER_DIGITAL_1 (Logical_XOR); REGISTER_DIGITAL_1 (Logical_XNOR); + REGISTER_DIGITAL_1 (dff_SR); REGISTER_DIGITAL_1 (jkff_SR); } From aeeb2deef5778d642e113525ad8a6881f9efffa8 Mon Sep 17 00:00:00 2001 From: Radvall Date: Fri, 31 Mar 2023 22:15:26 +0300 Subject: [PATCH 3/7] Add spice entry for T Flip Flop --- qucs/components/tff_SR.cpp | 23 ++++++++++++++++++++++- qucs/components/tff_SR.h | 1 + qucs/module.cpp | 2 +- 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/qucs/components/tff_SR.cpp b/qucs/components/tff_SR.cpp index dc13d7aaa..448df9ea7 100644 --- a/qucs/components/tff_SR.cpp +++ b/qucs/components/tff_SR.cpp @@ -18,6 +18,7 @@ #include "tff_SR.h" #include "node.h" #include "misc.h" +#include "extsimkernels/spicecompat.h" tff_SR::tff_SR() { @@ -36,7 +37,8 @@ tff_SR::tff_SR() tx = x1 + 4; ty = y2 + 4; Model = "tff_SR"; - Name = "Y"; + Name = "Y"; + SpiceModel = "A"; } Component * tff_SR::newOne() @@ -174,3 +176,22 @@ QString tff_SR::verilogCode( int ) " end\n"; return l; } + +QString tff_SR::spice_netlist(bool isXyce) +{ + if (isXyce) return QString(""); + + QString s = SpiceModel + Name; + QString tmp_model = "model_" + Name; + QString td = spicecompat::normalize_value(getProperty("Delay")->Value); + s += " " + Ports.at(1)->Connection->Name; + s += " " + Ports.at(2)->Connection->Name; + s += " " + Ports.at(0)->Connection->Name; + s += " " + Ports.at(3)->Connection->Name; + s += " " + Ports.at(5)->Connection->Name; + s += " " + Ports.at(4)->Connection->Name; + s += " " + tmp_model + "\n"; + s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n") + .arg(tmp_model).arg(td); + return s; +} diff --git a/qucs/components/tff_SR.h b/qucs/components/tff_SR.h index 044e0e5c3..2fc3a0823 100644 --- a/qucs/components/tff_SR.h +++ b/qucs/components/tff_SR.h @@ -24,6 +24,7 @@ class tff_SR : public Component void createSymbol(); QString vhdlCode(int); QString verilogCode(int); + QString spice_netlist(bool isXyce); }; #endif /* tff_SR_H */ diff --git a/qucs/module.cpp b/qucs/module.cpp index 95896ac82..bd1934d12 100644 --- a/qucs/module.cpp +++ b/qucs/module.cpp @@ -450,7 +450,6 @@ void Module::registerModules (void) { REGISTER_DIGITAL_1 (RS_FlipFlop); REGISTER_DIGITAL_1 (D_FlipFlop); REGISTER_DIGITAL_1 (JK_FlipFlop); - REGISTER_DIGITAL_1 (tff_SR); REGISTER_DIGITAL_1 (gatedDlatch); REGISTER_DIGITAL_1 (logic_0); REGISTER_DIGITAL_1 (logic_1); @@ -482,6 +481,7 @@ void Module::registerModules (void) { REGISTER_DIGITAL_1 (Logical_XNOR); REGISTER_DIGITAL_1 (dff_SR); REGISTER_DIGITAL_1 (jkff_SR); + REGISTER_DIGITAL_1 (tff_SR); } // file components From 130314b73f435ae85cd2fdabaa4748467343e8ae Mon Sep 17 00:00:00 2001 From: Radvall Date: Wed, 12 Apr 2023 19:14:52 +0300 Subject: [PATCH 4/7] Corrected T flip flop model name, rewrote pins defitition --- qucs/components/dff_SR.cpp | 16 ++++++++++------ qucs/components/jkff_SR.cpp | 18 +++++++++++------- qucs/components/tff_SR.cpp | 18 +++++++++++------- 3 files changed, 32 insertions(+), 20 deletions(-) diff --git a/qucs/components/dff_SR.cpp b/qucs/components/dff_SR.cpp index e5f9ea8e3..3006152a2 100644 --- a/qucs/components/dff_SR.cpp +++ b/qucs/components/dff_SR.cpp @@ -183,12 +183,16 @@ QString dff_SR::spice_netlist(bool isXyce) QString s = SpiceModel + Name; QString tmp_model = "model_" + Name; QString td = spicecompat::normalize_value(getProperty("Delay")->Value); - s += " " + Ports.at(1)->Connection->Name; - s += " " + Ports.at(2)->Connection->Name; - s += " " + Ports.at(0)->Connection->Name; - s += " " + Ports.at(3)->Connection->Name; - s += " " + Ports.at(5)->Connection->Name; - s += " " + Ports.at(4)->Connection->Name; + + QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name); + QString D = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name); + QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name); + QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name); + QString QB = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name); + QString Q = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name); + + s += " " + D + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB; + s += " " + tmp_model + "\n"; s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n") .arg(tmp_model).arg(td); diff --git a/qucs/components/jkff_SR.cpp b/qucs/components/jkff_SR.cpp index 1515a5e0d..789215b1d 100644 --- a/qucs/components/jkff_SR.cpp +++ b/qucs/components/jkff_SR.cpp @@ -193,13 +193,17 @@ QString jkff_SR::spice_netlist(bool isXyce) QString s = SpiceModel + Name; QString tmp_model = "model_" + Name; QString td = spicecompat::normalize_value(getProperty("Delay")->Value); - s += " " + Ports.at(1)->Connection->Name; - s += " " + Ports.at(3)->Connection->Name; - s += " " + Ports.at(2)->Connection->Name; - s += " " + Ports.at(0)->Connection->Name; - s += " " + Ports.at(4)->Connection->Name; - s += " " + Ports.at(6)->Connection->Name; - s += " " + Ports.at(5)->Connection->Name; + + QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name); + QString J = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name); + QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name); + QString K = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name); + QString RESET = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name); + QString QB = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name); + QString Q = spicecompat::normalize_node_name(Ports.at(6)->Connection->Name); + + s += " " + J + " " + K + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB; + s += " " + tmp_model + "\n"; s += QString(".model %1 d_jkff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n") .arg(tmp_model).arg(td); diff --git a/qucs/components/tff_SR.cpp b/qucs/components/tff_SR.cpp index 448df9ea7..92eae4d5c 100644 --- a/qucs/components/tff_SR.cpp +++ b/qucs/components/tff_SR.cpp @@ -184,14 +184,18 @@ QString tff_SR::spice_netlist(bool isXyce) QString s = SpiceModel + Name; QString tmp_model = "model_" + Name; QString td = spicecompat::normalize_value(getProperty("Delay")->Value); - s += " " + Ports.at(1)->Connection->Name; - s += " " + Ports.at(2)->Connection->Name; - s += " " + Ports.at(0)->Connection->Name; - s += " " + Ports.at(3)->Connection->Name; - s += " " + Ports.at(5)->Connection->Name; - s += " " + Ports.at(4)->Connection->Name; + + QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name); + QString T = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name); + QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name); + QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name); + QString QB = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name); + QString Q = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name); + + s += " " + T + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB; + s += " " + tmp_model + "\n"; - s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n") + s += QString(".model %1 d_tff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n") .arg(tmp_model).arg(td); return s; } From 27ee94bf9379c07b4e4ab51c2b7347f0a38980d0 Mon Sep 17 00:00:00 2001 From: Radvall Date: Fri, 14 Apr 2023 20:20:04 +0300 Subject: [PATCH 5/7] add spice entry for digital D flip flop --- qucs/components/d_flipflop.cpp | 29 ++++++++++++++++++++++++++++- qucs/components/d_flipflop.h | 1 + qucs/module.cpp | 2 +- 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/qucs/components/d_flipflop.cpp b/qucs/components/d_flipflop.cpp index f37d50fd5..9c720f8a4 100644 --- a/qucs/components/d_flipflop.cpp +++ b/qucs/components/d_flipflop.cpp @@ -17,10 +17,11 @@ #include "d_flipflop.h" #include "node.h" #include "misc.h" +#include "extsimkernels/spicecompat.h" D_FlipFlop::D_FlipFlop() { - Type = isDigitalComponent; + Type = isComponent; Description = QObject::tr("D flip flop with asynchronous reset"); Props.append(new Property("t", "0", false, QObject::tr("delay time"))); @@ -52,6 +53,7 @@ D_FlipFlop::D_FlipFlop() ty = y2+4; Model = "DFF"; Name = "Y"; + SpiceModel = "A"; } // ------------------------------------------------------- @@ -119,3 +121,28 @@ Element* D_FlipFlop::info(QString& Name, char* &BitmapFile, bool getNewOne) if(getNewOne) return new D_FlipFlop(); return 0; } + +QString D_FlipFlop::spice_netlist(bool isXyce) +{ + if (isXyce) return QString(""); + + QString s = SpiceModel + Name; + QString tmp_model = "model_" + Name; + QString td = spicecompat::normalize_value(getProperty("t")->Value); + + QString SET = "0"; + QString QB = "QB_" + Name; + QString D = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name); + QString CLK = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name); + QString Q = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name); + QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name); + + s += " " + D + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB; + + s += " " + tmp_model + "\n"; + s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n") + .arg(tmp_model).arg(td); + s += QString("C%1 NQ_%1 0 1N \n").arg(Name); // capacitor load for unused NQ pin + + return s; +} diff --git a/qucs/components/d_flipflop.h b/qucs/components/d_flipflop.h index d83bb5237..b216b7f3a 100644 --- a/qucs/components/d_flipflop.h +++ b/qucs/components/d_flipflop.h @@ -31,6 +31,7 @@ class D_FlipFlop : public Component { protected: QString vhdlCode(int); QString verilogCode(int); + QString spice_netlist(bool isXyce); }; #endif diff --git a/qucs/module.cpp b/qucs/module.cpp index bd1934d12..ffe3b825a 100644 --- a/qucs/module.cpp +++ b/qucs/module.cpp @@ -448,7 +448,6 @@ void Module::registerModules (void) { REGISTER_DIGITAL_1 (fa1b); REGISTER_DIGITAL_1 (fa2b); REGISTER_DIGITAL_1 (RS_FlipFlop); - REGISTER_DIGITAL_1 (D_FlipFlop); REGISTER_DIGITAL_1 (JK_FlipFlop); REGISTER_DIGITAL_1 (gatedDlatch); REGISTER_DIGITAL_1 (logic_0); @@ -479,6 +478,7 @@ void Module::registerModules (void) { REGISTER_DIGITAL_1 (Logical_AND); REGISTER_DIGITAL_1 (Logical_XOR); REGISTER_DIGITAL_1 (Logical_XNOR); + REGISTER_DIGITAL_1 (D_FlipFlop); REGISTER_DIGITAL_1 (dff_SR); REGISTER_DIGITAL_1 (jkff_SR); REGISTER_DIGITAL_1 (tff_SR); From d93fd33020ff6a634861b0203aea24d591c00ad6 Mon Sep 17 00:00:00 2001 From: Radvall Date: Thu, 20 Apr 2023 18:18:03 +0300 Subject: [PATCH 6/7] Add example --- examples/ngspice/flip_flops_truth_tables.sch | 218 +++++++++++++++++++ 1 file changed, 218 insertions(+) create mode 100644 examples/ngspice/flip_flops_truth_tables.sch diff --git a/examples/ngspice/flip_flops_truth_tables.sch b/examples/ngspice/flip_flops_truth_tables.sch new file mode 100644 index 000000000..cf65b3a94 --- /dev/null +++ b/examples/ngspice/flip_flops_truth_tables.sch @@ -0,0 +1,218 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <.TR TR3 1 710 1720 0 86 0 0 "lin" 1 "0" 1 "25 us" 1 "100" 1 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0> + + + + + + + + <1480 10 1490 10 "" 0 0 0 ""> + <1480 -30 1490 -30 "" 0 0 0 ""> + <1620 -90 1620 -20 "" 0 0 0 ""> + <1580 -90 1620 -90 "" 0 0 0 ""> + <1490 -90 1490 -30 "Q_JK" 1510 -30 37 ""> + <1490 -90 1520 -90 "" 0 0 0 ""> + <1490 10 1490 70 "NQ_JK" 1510 20 27 ""> + <1490 70 1520 70 "" 0 0 0 ""> + <1580 70 1620 70 "" 0 0 0 ""> + <1620 70 1620 140 "" 0 0 0 ""> + <1290 -10 1380 -10 "clc_JK" 1294 -40 60 ""> + <1290 -10 1290 10 "" 0 0 0 ""> + <1380 10 1380 110 "" 0 0 0 ""> + <1290 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120 "" 0 0 0 ""> + <2070 60 2160 60 "clc_T" 2100 10 11 ""> + <2210 -130 2210 -20 "" 0 0 0 ""> + <2210 -130 2250 -130 "set_T" 2240 -170 6 ""> + <660 -30 670 -30 "" 0 0 0 ""> + <670 -100 670 -30 "Q_D" 690 -30 47 ""> + <670 -100 700 -100 "" 0 0 0 ""> + <800 -100 800 -30 "" 0 0 0 ""> + <760 -100 800 -100 "" 0 0 0 ""> + <660 10 700 10 "" 0 0 0 ""> + <760 10 800 10 "" 0 0 0 ""> + <800 10 800 20 "" 0 0 0 ""> + <490 10 560 10 "clc_D" 540 -20 0 ""> + <610 -110 610 -70 "" 0 0 0 ""> + <380 -110 610 -110 "set_D" 610 -150 198 ""> + <410 -30 560 -30 "D" 500 -60 60 ""> + <410 -30 410 -20 "" 0 0 0 ""> + <610 50 610 110 "" 0 0 0 ""> + <380 110 610 110 "reset_D" 570 130 170 ""> + <2210 100 2210 130 "reset_T" 2121 130 17 ""> + <2360 120 2400 120 "" 0 0 0 ""> + <2400 120 2400 180 "" 0 0 0 ""> + <700 10 700 10 "NQ_D" 651 30 0 ""> + + + + <"ngspice/tran.v(q_d)" #0900fe 0 3 0 0 0> + + + <"ngspice/tran.v(d)" #0900fe 0 3 0 0 0> + + + <"ngspice/tran.v(clc_d)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(set_d)" #0900fe 0 3 0 0 0> + + + <"ngspice/tran.v(reset_d)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(nq_d)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(clc_t)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(clc_jk)" #0900fd 0 3 0 0 0> + + + <"ngspice/tran.v(set_jk)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(reset_jk)" #0900fd 0 3 0 0 0> + + + <"ngspice/tran.v(q_jk)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(nq_jk)" #0900fd 0 3 0 0 0> + + + <"ngspice/tran.v(j)" #0900fe 0 3 0 0 0> + + + <"ngspice/tran.v(k)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(nq_t)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(q_t)" #0900fd 0 3 0 0 0> + + + <"ngspice/tran.v(reset_t)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(set_t)" #0900fd 0 3 0 0 0> + + + <"ngspice/tran.v(q_rs)" #0900fd 0 3 0 0 0> + + + <"ngspice/tran.v(clc_rs)" #ff0000 0 3 0 0 0> + + + <"ngspice/tran.v(t)" #0900fd 0 3 0 0 0> + + + <"ngspice/tran.v(d)" #0900fd 0 3 0 0 0> + + + + + + + + + + + + + + + + From 4ab7bc4a5c45b6e946fef3a2975c73abff74413c Mon Sep 17 00:00:00 2001 From: Radvall Date: Thu, 20 Apr 2023 18:45:12 +0300 Subject: [PATCH 7/7] fixed load capacitor node name --- qucs/components/d_flipflop.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qucs/components/d_flipflop.cpp b/qucs/components/d_flipflop.cpp index 9c720f8a4..3057c73f2 100644 --- a/qucs/components/d_flipflop.cpp +++ b/qucs/components/d_flipflop.cpp @@ -142,7 +142,7 @@ QString D_FlipFlop::spice_netlist(bool isXyce) s += " " + tmp_model + "\n"; s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n") .arg(tmp_model).arg(td); - s += QString("C%1 NQ_%1 0 1N \n").arg(Name); // capacitor load for unused NQ pin + s += QString("C%1 QB_%1 0 1e-9 \n").arg(Name); // capacitor load for unused QB pin return s; }