From c247036eac5316d563087b5fde51e239b274fcfe Mon Sep 17 00:00:00 2001 From: HMPerson1 Date: Thu, 15 Mar 2018 18:31:25 -0400 Subject: [PATCH] Rename `Jump` to `Terminator` --- src/middle/ir_reader/lowering.rs | 8 ++++---- src/middle/ir_reader/parser.lalrpop | 12 ++++++------ src/middle/ir_reader/simple_ast.rs | 10 +++++----- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/middle/ir_reader/lowering.rs b/src/middle/ir_reader/lowering.rs index e8948598..944fd1a9 100644 --- a/src/middle/ir_reader/lowering.rs +++ b/src/middle/ir_reader/lowering.rs @@ -155,11 +155,11 @@ impl<'a> LowerSsa<'a> { let next_node = opt_next_addr.map_or(Ok(self.exit_node), |a| self.block_at(a))?; match sbb.jump { - Some(sast::Jump::Uncond(tgt)) => { + Some(sast::Terminator::JmpUncond(tgt)) => { let tgt_bb = self.block_at(tgt)?; self.ssa.insert_control_edge(bb, tgt_bb, UNCOND_EDGE); } - Some(sast::Jump::Cond(sel_sop, if_tgt, opt_else_tgt)) => { + Some(sast::Terminator::JmpCond(sel_sop, if_tgt, opt_else_tgt)) => { let sel_op = self.lower_operand(sel_sop)?; let if_bb = self.block_at(if_tgt)?; let else_bb = opt_else_tgt.map_or(Ok(next_node), |a| self.block_at(a))?; @@ -167,13 +167,13 @@ impl<'a> LowerSsa<'a> { self.ssa.insert_control_edge(bb, if_bb, TRUE_EDGE); self.ssa.insert_control_edge(bb, else_bb, FALSE_EDGE); } - Some(sast::Jump::Indirect(sel_sop)) => { + Some(sast::Terminator::JmpIndirect(sel_sop)) => { let sel_op = self.lower_operand(sel_sop)?; self.ssa.set_selector(sel_op, bb); self.ssa .insert_control_edge(bb, self.exit_node, UNCOND_EDGE); } - Some(sast::Jump::Unreachable) => { + Some(sast::Terminator::Unreachable) => { // nothing to do } None => { diff --git a/src/middle/ir_reader/parser.lalrpop b/src/middle/ir_reader/parser.lalrpop index 0eae9811..8e6f2076 100644 --- a/src/middle/ir_reader/parser.lalrpop +++ b/src/middle/ir_reader/parser.lalrpop @@ -21,7 +21,7 @@ RegisterList: Vec = "registers: " > ";" => <>; BasicBlock: BasicBlock = - => BasicBlock { <> }; + => BasicBlock { <> }; BBHeader: ir::MAddress = "bb_" "(" ")" ":" => <>; @@ -58,11 +58,11 @@ Expr: Expr = { "(" ")" => Expr::Resize(<>), }; -Jump: Jump = { - "JMP" => Jump::Uncond(<>), - "JMP" "IF" <("ELSE" )?> => Jump::Cond(<>), - "JMP" "TO" => Jump::Indirect(<>), - "UNREACHABLE" => Jump::Unreachable, +Terminator: Terminator = { + "JMP" => Terminator::JmpUncond(<>), + "JMP" "IF" <("ELSE" )?> => Terminator::JmpCond(<>), + "JMP" "TO" => Terminator::JmpIndirect(<>), + "UNREACHABLE" => Terminator::Unreachable, }; FinalRegState: Vec<(PhysReg, Operand)> = diff --git a/src/middle/ir_reader/simple_ast.rs b/src/middle/ir_reader/simple_ast.rs index 8dcadd70..21b56dca 100644 --- a/src/middle/ir_reader/simple_ast.rs +++ b/src/middle/ir_reader/simple_ast.rs @@ -19,7 +19,7 @@ pub struct Function { pub struct BasicBlock { pub addr: ir::MAddress, pub ops: Vec, - pub jump: Option, + pub jump: Option, } #[derive(Debug)] @@ -64,10 +64,10 @@ pub enum Operand { } #[derive(Debug)] -pub enum Jump { - Uncond(ir::MAddress), - Cond(Operand, ir::MAddress, Option), - Indirect(Operand), +pub enum Terminator { + JmpUncond(ir::MAddress), + JmpCond(Operand, ir::MAddress, Option), + JmpIndirect(Operand), Unreachable, }