diff --git a/src/hwinit/clock.c b/src/hwinit/clock.c index c959749..12e8c9b 100644 --- a/src/hwinit/clock.c +++ b/src/hwinit/clock.c @@ -51,14 +51,14 @@ static clock_t _clock_coresight = { 0xC, 0x18, 0x1D4, 9, 0, 4}; void clock_enable(const clock_t *clk) { //Put clock into reset. - CLOCK(clk->reset) = CLOCK(clk->reset) & ~(1 << clk->index) | (1 << clk->index); + CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index); //Disable. CLOCK(clk->enable) &= ~(1 << clk->index); //Configure clock source if required. if (clk->source) CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29); //Enable. - CLOCK(clk->enable) = CLOCK(clk->enable) & ~(1 << clk->index) | (1 << clk->index); + CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index); //Take clock off reset. CLOCK(clk->reset) &= ~(1 << clk->index); } @@ -66,14 +66,14 @@ void clock_enable(const clock_t *clk) void clock_disable(const clock_t *clk) { //Put clock into reset. - CLOCK(clk->reset) = CLOCK(clk->reset) & ~(1 << clk->index) | (1 << clk->index); + CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index); //Disable. CLOCK(clk->enable) &= ~(1 << clk->index); } void clock_enable_fuse(u32 enable) { - CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF | ((enable & 1) << 28) & 0x10000000; + CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = (CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF) | (((enable & 1) << 28) & 0x10000000); } void clock_enable_uart(u32 idx) @@ -144,9 +144,9 @@ void clock_disable_sor1() void clock_enable_kfuse() { //clock_enable(&_clock_kfuse); - CLOCK(0x8) = CLOCK(0x8) & 0xFFFFFEFF | 0x100; + CLOCK(0x8) = (CLOCK(0x8) & 0xFFFFFEFF) | 0x100; CLOCK(0x14) &= 0xFFFFFEFF; - CLOCK(0x14) = CLOCK(0x14) & 0xFFFFFEFF | 0x100; + CLOCK(0x14) = (CLOCK(0x14) & 0xFFFFFEFF) | 0x100; sleep(10); CLOCK(0x8) &= 0xFFFFFEFF; sleep(20); @@ -259,7 +259,7 @@ static int _clock_sdmmc_is_enabled(u32 id) return 0; } -static int _clock_sdmmc_set_enable(u32 id) +static void _clock_sdmmc_set_enable(u32 id) { switch (id) { @@ -274,7 +274,7 @@ static int _clock_sdmmc_set_enable(u32 id) } } -static int _clock_sdmmc_clear_enable(u32 id) +static void _clock_sdmmc_clear_enable(u32 id) { switch (id) { diff --git a/src/hwinit/cluster.c b/src/hwinit/cluster.c index dcb1e2e..4ba10af 100644 --- a/src/hwinit/cluster.c +++ b/src/hwinit/cluster.c @@ -77,15 +77,15 @@ void cluster_boot_cpu0(u32 entry) sleep(2); CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02; CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02; - CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF | 0x40000; + CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000; CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x40404E02; } while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x8000000)) ; //Configure MSELECT source and enable clock. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00 | 6; - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & 0xFFFFFFF7 | 8; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6; + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & 0xFFFFFFF7) | 8; //Configure initial CPU clock frequency and enable clock. CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888; diff --git a/src/hwinit/di.c b/src/hwinit/di.c index d1f2280..3ee135e 100644 --- a/src/hwinit/di.c +++ b/src/hwinit/di.c @@ -60,19 +60,19 @@ void display_init() PINMUX_AUX(0x200) &= 0xFFFFFFEF; PINMUX_AUX(0x204) &= 0xFFFFFFEF; - GPIO_3(0x00) = GPIO_3(0x00) & 0xFFFFFFFC | 0x3; - GPIO_3(0x10) = GPIO_3(0x10) & 0xFFFFFFFC | 0x3; - GPIO_3(0x20) = GPIO_3(0x20) & 0xFFFFFFFE | 0x1; + GPIO_3(0x00) = (GPIO_3(0x00) & 0xFFFFFFFC) | 0x3; + GPIO_3(0x10) = (GPIO_3(0x10) & 0xFFFFFFFC) | 0x3; + GPIO_3(0x20) = (GPIO_3(0x20) & 0xFFFFFFFE) | 0x1; sleep(10000u); - GPIO_3(0x20) = GPIO_3(0x20) & 0xFFFFFFFD | 0x2; + GPIO_3(0x20) = (GPIO_3(0x20) & 0xFFFFFFFD) | 0x2; sleep(10000); - GPIO_6(0x04) = GPIO_6(0x04) & 0xFFFFFFF8 | 0x7; - GPIO_6(0x14) = GPIO_6(0x14) & 0xFFFFFFF8 | 0x7; - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFD | 0x2; + GPIO_6(0x04) = (GPIO_6(0x04) & 0xFFFFFFF8) | 0x7; + GPIO_6(0x14) = (GPIO_6(0x14) & 0xFFFFFFF8) | 0x7; + GPIO_6(0x24) = (GPIO_6(0x24) & 0xFFFFFFFD) | 0x2; //Config display interface and display. MIPI_CAL(0x60) = 0; @@ -83,7 +83,7 @@ void display_init() sleep(10000); - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFB | 0x4; + GPIO_6(0x24) = (GPIO_6(0x24) & 0xFFFFFFFB) | 0x4; sleep(60000); @@ -180,7 +180,7 @@ void display_end() GPIO_6(0x04) &= 0xFFFFFFFE; - PINMUX_AUX(0x1FC) = PINMUX_AUX(0x1FC) & 0xFFFFFFEF | 0x10; + PINMUX_AUX(0x1FC) = (PINMUX_AUX(0x1FC) & 0xFFFFFFEF) | 0x10; PINMUX_AUX(0x1FC) = (PINMUX_AUX(0x1FC) >> 2) << 2 | 1; } @@ -193,11 +193,11 @@ void display_color_screen(u32 color) DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0; DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0; DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE | 1; + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | 1; sleep(35000); - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFE | 1; + GPIO_6(0x24) = (GPIO_6(0x24) & 0xFFFFFFFE) | 1; } u32 *display_init_framebuffer(u32 *fb) @@ -207,7 +207,12 @@ u32 *display_init_framebuffer(u32 *fb) sleep(35000); - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFE | 1; + GPIO_6(0x24) = (GPIO_6(0x24) & 0xFFFFFFFE) | 1; return (u32 *)0xC0000000; } + +void display_enable_backlight(u32 on) +{ + GPIO_6(0x24) = (GPIO_6(0x24) & 0xFFFFFFFE) | (!!on); +} \ No newline at end of file diff --git a/src/hwinit/di.h b/src/hwinit/di.h index 29e3ebf..b5a0fd3 100644 --- a/src/hwinit/di.h +++ b/src/hwinit/di.h @@ -69,4 +69,7 @@ void display_color_screen(u32 color); /*! Init display in full 1280x720 resolution (32bpp, line stride 768, framebuffer size = 1280*768*4 bytes). */ u32 *display_init_framebuffer(); +/*! Enable or disable the backlight. Should only be called when the screen is completely set up, to avoid flickering. */ +void display_enable_backlight(u32 on); + #endif diff --git a/src/hwinit/hwinit.c b/src/hwinit/hwinit.c index b72c2af..5fef665 100644 --- a/src/hwinit/hwinit.c +++ b/src/hwinit/hwinit.c @@ -22,23 +22,25 @@ #include "mc.h" #include "t210.h" #include "pmc.h" +#include "gpio.h" #include "pinmux.h" +#include "max77620.h" #include "fuse.h" #include "util.h" void config_oscillators() { - CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3 | 4; + CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; SYSCTR0(SYSCTR0_CNTFID0) = 19200000; TMR(0x14) = 0x45F; CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; - PMC(APBDEV_PMC_OSC_EDPD_OVER) = PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81 | 0xE; - PMC(APBDEV_PMC_OSC_EDPD_OVER) = PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF | 0x400000; - PMC(APBDEV_PMC_CNTRL2) = PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF | 0x1000; - PMC(APBDEV_PMC_SCRATCH188) = PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF | 0x2000000; + PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; + PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | 0x400000; + PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | 0x1000; + PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | 0x2000000; CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; - PMC(APBDEV_PMC_TSC_MULT) = PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000 | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz) + PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz) CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; @@ -119,9 +121,9 @@ void mbist_workaround() CLOCK(0x554) = 0; CLOCK(0xD0) &= 0x1F7FFFFF; CLOCK(0x410) &= 0xFFFF3FFF; - CLOCK(0x148) = CLOCK(0x148) & 0x1FFFFFFF | 0x80000000; - CLOCK(0x180) = CLOCK(0x180) & 0x1FFFFFFF | 0x80000000; - CLOCK(0x6A0) = CLOCK(0x6A0) & 0x1FFFFFFF | 0x80000000; + CLOCK(0x148) = (CLOCK(0x148) & 0x1FFFFFFF) | 0x80000000; + CLOCK(0x180) = (CLOCK(0x180) & 0x1FFFFFFF) | 0x80000000; + CLOCK(0x6A0) = (CLOCK(0x6A0) & 0x1FFFFFFF) | 0x80000000; } void config_hw() @@ -172,7 +174,7 @@ void config_hw() config_pmc_scratch(); - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888 | 0x3333; + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; mc_config_carveout(); diff --git a/src/hwinit/i2c.c b/src/hwinit/i2c.c index cad793f..00feb35 100644 --- a/src/hwinit/i2c.c +++ b/src/hwinit/i2c.c @@ -46,7 +46,7 @@ static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size) base[0] = (2 * size - 2) | 0x2800; //Set size and send mode. _i2c_wait(base); //Kick transaction. - base[0] = base[0] & 0xFFFFFDFF | 0x200; + base[0] = (base[0] & 0xFFFFFDFF) | 0x200; while (base[7] & 0x100) ; @@ -66,7 +66,7 @@ static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x) base[0] = (2 * size - 2) | 0x2840; //Set size and recv mode. _i2c_wait(base); //Kick transaction. - base[0] = base[0] & 0xFFFFFDFF | 0x200; + base[0] = (base[0] & 0xFFFFFDFF) | 0x200; while (base[7] & 0x100) ; @@ -94,7 +94,7 @@ void i2c_init(u32 idx) break; } - vu32 dummy = base[0x22]; + (void)base[0x22]; base[0x1A] = base[0x1A]; } @@ -108,7 +108,7 @@ u32 i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size) tmp[0] = y; memcpy(tmp + 1, buf, size); - _i2c_send_pkt(idx, x, tmp, size + 1); + return _i2c_send_pkt(idx, x, tmp, size + 1); } int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y) @@ -121,7 +121,7 @@ int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y) u32 i2c_send_byte(u32 idx, u32 x, u32 y, u8 b) { - i2c_send_buf_small(idx, x, y, &b, 1); + return i2c_send_buf_small(idx, x, y, &b, 1); } u8 i2c_recv_byte(u32 idx, u32 x, u32 y) diff --git a/src/hwinit/max7762x.c b/src/hwinit/max7762x.c index 5e8d923..67caaf2 100644 --- a/src/hwinit/max7762x.c +++ b/src/hwinit/max7762x.c @@ -19,11 +19,6 @@ #include "i2c.h" #include "util.h" -#include "gfx.h" -extern gfx_ctxt_t gfx_ctxt; -extern gfx_con_t gfx_con; -#define DPRINTF(...) gfx_printf(&gfx_con, __VA_ARGS__) - #define REGULATOR_SD 0 #define REGULATOR_LDO 1 diff --git a/src/hwinit/mc.c b/src/hwinit/mc.c index 1c8cc2a..a4cec19 100644 --- a/src/hwinit/mc.c +++ b/src/hwinit/mc.c @@ -102,7 +102,7 @@ void mc_config_carveout() void mc_enable_ahb_redirect() { - CLOCK(0x3A4) = CLOCK(0x3A4) & 0xFFF7FFFF | 0x80000; + CLOCK(0x3A4) = (CLOCK(0x3A4) & 0xFFF7FFFF) | 0x80000; //MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE; MC(MC_IRAM_BOM) = 0x40000000; MC(MC_IRAM_TOM) = 0x4003F000; @@ -119,13 +119,13 @@ void mc_disable_ahb_redirect() void mc_enable() { - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF | 0x40000000; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | 0x40000000; //Enable MIPI CAL clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF | 0x2000000; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF) | 0x2000000; //Enable MC clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE | 1; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE) | 1; //Enable EMC DLL clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF | 0x4000; + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF) | 0x4000; CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x2000001; //Clear EMC and MC reset. sleep(5); diff --git a/src/hwinit/sdmmc.c b/src/hwinit/sdmmc.c index 5e18ec4..d76f693 100644 --- a/src/hwinit/sdmmc.c +++ b/src/hwinit/sdmmc.c @@ -19,13 +19,14 @@ #include "mmc.h" #include "sd.h" #include "util.h" -#include "heap.h" +#include "lib/heap.h" -/*#include "gfx.h" -extern gfx_ctxt_t gfx_ctxt; -extern gfx_con_t gfx_con; -#define DPRINTF(...) gfx_printf(&gfx_con, __VA_ARGS__)*/ +#ifdef SDMMC_DEBUGGING +#include "lib/printk.h" +#define DPRINTF(...) printk(__VA_ARGS__) +#else #define DPRINTF(...) +#endif static inline u32 unstuff_bits(u32 *resp, u32 start, u32 size) { @@ -174,6 +175,7 @@ static int _sdmmc_storage_readwrite(sdmmc_storage_t *storage, u32 sector, u32 nu num_sectors -= blkcnt; bbuf += 512 * blkcnt; } + return 1; } int sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf) @@ -350,9 +352,8 @@ static int _mmc_storage_enable_highspeed(sdmmc_storage_t *storage, u32 card_type return _mmc_storage_enable_HS400(storage); if (sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_8 || - sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_4 - && card_type & EXT_CSD_CARD_TYPE_HS200_1_8V - && (type == 4 || type == 3)) + (sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_4 && + (card_type & EXT_CSD_CARD_TYPE_HS200_1_8V) && (type == 4 || type == 3))) return _mmc_storage_enable_HS200(storage); out:; @@ -498,7 +499,7 @@ static int _sd_storage_send_if_cond(sdmmc_storage_t *storage) static int _sd_storage_get_op_cond_once(sdmmc_storage_t *storage, u32 *cond, int is_version_1, int supports_low_voltage) { sdmmc_cmd_t cmdbuf; - u32 arg = (((~is_version_1 & 1) << 28) & 0xBFFFFFFF | ((~is_version_1 & 1) << 30)) & 0xFEFFFFFF | ((supports_low_voltage & ~is_version_1 & 1) << 24) | 0x100000; + u32 arg = ((((~is_version_1 & 1) << 28) & 0xBFFFFFFF) | ((((~is_version_1 & 1) << 30)) & 0xFEFFFFFF)) | ((supports_low_voltage & ~is_version_1 & 1) << 24) | 0x100000; sdmmc_init_cmd(&cmdbuf, SD_APP_OP_COND, arg, SDMMC_RSP_TYPE_3, 0); if (!_sd_storage_execute_app_cmd(storage, 0x10, is_version_1 ? 0x400000 : 0, &cmdbuf, 0, 0)) return 0; @@ -645,12 +646,12 @@ int _sd_storage_enable_highspeed(sdmmc_storage_t *storage, u32 hs_type, u8 *buf) if (type_out != hs_type) return 0; - if (((u16)buf[0] << 8) | buf[1] < 0x320) + if ((((u16)buf[0] << 8) | buf[1]) < 0x320) { if (!_sd_storage_switch(storage, buf, 1, hs_type)) return 0; - if (type_out != buf[16] & 0xF) + if (type_out != (buf[16] & 0xF)) return 0; } @@ -815,7 +816,7 @@ int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32 } DPRINTF("[sd] enabled highspeed (low voltage)\n"); } - else if (type != 6 && storage->scr[0] & 0xF != 0) + else if (type != 6 && (storage->scr[0] & 0xF) != 0) { if (!_sd_storage_enable_highspeed_high_volt(storage, buf)) { diff --git a/src/hwinit/sdmmc_driver.c b/src/hwinit/sdmmc_driver.c index e5c9b37..42e8a61 100644 --- a/src/hwinit/sdmmc_driver.c +++ b/src/hwinit/sdmmc_driver.c @@ -123,7 +123,7 @@ static int _sdmmc_config_ven_ceata_clk(sdmmc_t *sdmmc, u32 id) static const u32 tap_values[] = { 4, 0, 3, 0 }; tap_val = tap_values[sdmmc->id]; } - sdmmc->regs->venclkctl = sdmmc->regs->venclkctl & 0xFF00FFFF | (tap_val << 16); + sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xFF00FFFF) | (tap_val << 16); return 1; } @@ -596,7 +596,7 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power) break; } - sdmmc->regs->autocalcfg = ((sdmmc->regs->autocalcfg & 0xFFFF80FF | (off_pd << 8)) >> 7 << 7) | off_pu; + sdmmc->regs->autocalcfg = (((sdmmc->regs->autocalcfg & 0xFFFF80FF) | (off_pd << 8)) >> 7 << 7) | off_pu; return 1; } diff --git a/src/hwinit/sdram.c b/src/hwinit/sdram.c index d8cbccb..6cef998 100644 --- a/src/hwinit/sdram.c +++ b/src/hwinit/sdram.c @@ -27,7 +27,7 @@ #define CONFIG_SDRAM_COMPRESS_CFG #ifdef CONFIG_SDRAM_COMPRESS_CFG -#include "lz.h" +#include "lib/lz.h" #include "sdram_lz.inl" #else #include "sdram.inl" @@ -64,7 +64,7 @@ static void _sdram_config(const sdram_params_t *params) sleep(10); break_nosleep: - CLOCK(0x19C) = (params->mc_emem_arb_misc0 >> 11) & 0x10000 | params->emc_clock_source & 0xFFFEFFFF; + CLOCK(0x19C) = ((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF); if (params->emc_clock_source_dll) CLOCK(0x664) = params->emc_clock_source_dll; if (params->clear_clock2_mc1) @@ -97,7 +97,7 @@ static void _sdram_config(const sdram_params_t *params) EMC(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0; EMC(EMC_PMACRO_BRICK_MAPPING_1) = params->emc_pmacro_brick_mapping1; EMC(EMC_PMACRO_BRICK_MAPPING_2) = params->emc_pmacro_brick_mapping2; - EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1 & 0x1120112 | 0x1EED1EED; + EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = (params->emc_pmacro_brick_ctrl_rfu1 & 0x1120112) | 0x1EED1EED; EMC(EMC_CONFIG_SAMPLE_DELAY) = params->emc_config_sample_delay; EMC(EMC_FBIO_CFG8) = params->emc_fbio_cfg8; EMC(EMC_SWIZZLE_RANK0_BYTE0) = params->emc_swizzle_rank0_byte0; @@ -142,10 +142,10 @@ static void _sdram_config(const sdram_params_t *params) EMC(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1; EMC(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2; EMC(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3; - EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1 & 0x1BF01BF | 0x1E401E40; + EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = (params->emc_pmacro_brick_ctrl_rfu1 & 0x1BF01BF) | 0x1E401E40; EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; - EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F; + EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = (params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F); EMC(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd; EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0; EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; @@ -232,7 +232,7 @@ static void _sdram_config(const sdram_params_t *params) EMC(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0; EMC(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1; EMC(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2; - EMC(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl & 1 | 0xE; + EMC(EMC_PMACRO_COMMON_PAD_TX_CTRL) = (params->emc_pmacro_common_pad_tx_ctrl & 1) | 0xE; if (params->emc_bct_spare4) *(vu32 *)params->emc_bct_spare4 = params->emc_bct_spare5; EMC(EMC_TIMING_CONTROL) = 1; @@ -386,7 +386,7 @@ static void _sdram_config(const sdram_params_t *params) EMC(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3; EMC(EMC_ACPD_CONTROL) = params->emc_acpd_control; EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; - EMC(EMC_CFG) = params->emc_cfg & 0xE | 0x3C00000; + EMC(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000; if (params->boot_rom_patch_control & 0x80000000) { *(vu32 *)(4 * (params->boot_rom_patch_control + 0x1C000000)) = params->boot_rom_patch_data; @@ -481,7 +481,7 @@ static void _sdram_config(const sdram_params_t *params) EMC(EMC_TIMING_CONTROL) = 1; EMC(EMC_CFG_PIPE_CLK) = params->emc_cfg_pipe_clk; EMC(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->emc_fdpd_ctrl_cmd_no_ramp; - SYSREG(AHB_ARBITRATION_XBAR_CTRL) = SYSREG(AHB_ARBITRATION_XBAR_CTRL) & 0xFFFEFFFF | ((params->ahb_arbitration_xbar_ctrl_meminit_done & 0xFFFF) << 16); + SYSREG(AHB_ARBITRATION_XBAR_CTRL) = (SYSREG(AHB_ARBITRATION_XBAR_CTRL) & 0xFFFEFFFF) | ((params->ahb_arbitration_xbar_ctrl_meminit_done & 0xFFFF) << 16); MC(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access; MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl;