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lapic: Centralize LAPIC configuration

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1 parent a15a5b3 commit 4d08e03847639314826048c33a5887a4bd35074f Sepherosa Ziehau committed Mar 19, 2011
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20 sys/platform/pc32/apic/ioapic_abi.c
@@ -520,7 +520,6 @@ static void
ioapic_finalize(void)
{
u_long ef;
- uint32_t temp;
KKASSERT(MachIntrABI.type == MACHINTR_ICU);
KKASSERT(apic_io_enable);
@@ -535,15 +534,6 @@ ioapic_finalize(void)
outb(0x23, 0x01); /* disconnect 8259 */
}
- /*
- * Setup LINT0 (the 8259 'virtual wire' connection). We
- * mask the interrupt, completing the disconnection of the
- * 8259.
- */
- temp = lapic.lvt_lint0;
- temp |= APIC_LVT_MASKED;
- lapic.lvt_lint0 = temp;
-
crit_enter();
ef = read_eflags();
@@ -561,16 +551,6 @@ ioapic_finalize(void)
MachIntrABI.cleanup();
crit_exit();
-
- /*
- * Setup LINT1 to handle NMI
- */
- temp = lapic.lvt_lint1;
- temp &= ~APIC_LVT_MASKED;
- lapic.lvt_lint1 = temp;
-
- if (bootverbose)
- apic_dump("ioapic_finalize()");
}
/*
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20 sys/platform/pc32/apic/mpapic.c
@@ -165,26 +165,38 @@ lapic_init(boolean_t bsp)
*
* Must be setup edge triggered, active high.
*
+ * Disable LINT0 on BSP, if I/O APIC is enabled.
+ *
* Disable LINT0 on the APs. It doesn't matter what delivery
* mode we use because we leave it masked.
*/
temp = lapic.lvt_lint0;
temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
- if (bsp)
+ if (bsp) {
temp |= APIC_LVT_DM_EXTINT;
- else
+ if (apic_io_enable)
+ temp |= APIC_LVT_MASKED;
+ } else {
temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
+ }
lapic.lvt_lint0 = temp;
/*
- * Setup LINT1 as NMI, masked till later.
- * Edge trigger, active high.
+ * Setup LINT1 as NMI.
+ *
+ * Must be setup edge trigger, active high.
+ *
+ * Enable LINT1 on BSP, if I/O APIC is enabled.
+ *
+ * Disable LINT1 on the APs.
*/
temp = lapic.lvt_lint1;
temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
+ if (bsp && apic_io_enable)
+ temp &= ~APIC_LVT_MASKED;
lapic.lvt_lint1 = temp;
/*
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20 sys/platform/pc64/apic/ioapic_abi.c
@@ -520,7 +520,6 @@ static void
ioapic_finalize(void)
{
register_t ef;
- uint32_t temp;
KKASSERT(MachIntrABI.type == MACHINTR_ICU);
KKASSERT(apic_io_enable);
@@ -535,15 +534,6 @@ ioapic_finalize(void)
outb(0x23, 0x01); /* disconnect 8259 */
}
- /*
- * Setup LINT0 (the 8259 'virtual wire' connection). We
- * mask the interrupt, completing the disconnection of the
- * 8259.
- */
- temp = lapic->lvt_lint0;
- temp |= APIC_LVT_MASKED;
- lapic->lvt_lint0 = temp;
-
crit_enter();
ef = read_rflags();
@@ -561,16 +551,6 @@ ioapic_finalize(void)
MachIntrABI.cleanup();
crit_exit();
-
- /*
- * Setup LINT1 to handle an NMI
- */
- temp = lapic->lvt_lint1;
- temp &= ~APIC_LVT_MASKED;
- lapic->lvt_lint1 = temp;
-
- if (bootverbose)
- apic_dump("ioapic_finalize()");
}
/*
View
20 sys/platform/pc64/apic/mpapic.c
@@ -172,26 +172,38 @@ lapic_init(boolean_t bsp)
*
* Must be setup edge triggered, active high.
*
+ * Disable LINT0 on BSP, if I/O APIC is enabled.
+ *
* Disable LINT0 on the APs. It doesn't matter what delivery
* mode we use because we leave it masked.
*/
temp = lapic->lvt_lint0;
temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
- if (bsp)
+ if (bsp) {
temp |= APIC_LVT_DM_EXTINT;
- else
+ if (apic_io_enable)
+ temp |= APIC_LVT_MASKED;
+ } else {
temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
+ }
lapic->lvt_lint0 = temp;
/*
- * Setup LINT1 as NMI, masked till later.
- * Edge trigger, active high.
+ * Setup LINT1 as NMI.
+ *
+ * Must be setup edge trigger, active high.
+ *
+ * Enable LINT1 on BSP, if I/O APIC is enabled.
+ *
+ * Disable LINT1 on the APs.
*/
temp = lapic->lvt_lint1;
temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
+ if (bsp && apic_io_enable)
+ temp &= ~APIC_LVT_MASKED;
lapic->lvt_lint1 = temp;
/*

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