Skip to content
Browse files

lapic: Move LAPIC related vector installation into lapic_init()

  • Loading branch information...
1 parent 5ddeabb commit dbfb3a5a3fb078648f010950aea99ab99371fd92 Sepherosa Ziehau committed Mar 19, 2011
View
28 sys/platform/pc32/apic/mpapic.c
@@ -130,6 +130,34 @@ lapic_init(boolean_t bsp)
u_int temp;
/*
+ * Install vectors
+ *
+ * Since IDT is shared between BSP and APs, these vectors
+ * only need to be installed once; we do it on BSP.
+ */
+ if (bsp) {
+ /* Install a 'Spurious INTerrupt' vector */
+ setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
+ SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+
+ /* Install an inter-CPU IPI for TLB invalidation */
+ setidt(XINVLTLB_OFFSET, Xinvltlb,
+ SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+
+ /* Install an inter-CPU IPI for IPIQ messaging */
+ setidt(XIPIQ_OFFSET, Xipiq,
+ SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+
+ /* Install a timer vector */
+ setidt(XTIMER_OFFSET, Xtimer,
+ SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+
+ /* Install an inter-CPU IPI for CPU stop/restart */
+ setidt(XCPUSTOP_OFFSET, Xcpustop,
+ SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+ }
+
+ /*
* Setup LINT0 as ExtINT on the BSP. This is theoretically an
* aggregate interrupt input from the 8259. The INTA cycle
* will be routed to the external controller (the 8259) which
View
24 sys/platform/pc32/i386/mp_machdep.c
@@ -689,30 +689,6 @@ if (apic_io_enable && ioapic_use_old) {
}
- /*
- * These are required for SMP operation
- */
-
- /* install a 'Spurious INTerrupt' vector */
- setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
- SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-
- /* install an inter-CPU IPI for TLB invalidation */
- setidt(XINVLTLB_OFFSET, Xinvltlb,
- SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-
- /* install an inter-CPU IPI for IPIQ messaging */
- setidt(XIPIQ_OFFSET, Xipiq,
- SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-
- /* install a timer vector */
- setidt(XTIMER_OFFSET, Xtimer,
- SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-
- /* install an inter-CPU IPI for CPU stop/restart */
- setidt(XCPUSTOP_OFFSET, Xcpustop,
- SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-
/* start each Application Processor */
start_all_aps(boot_addr);
}
View
28 sys/platform/pc64/apic/mpapic.c
@@ -137,6 +137,34 @@ lapic_init(boolean_t bsp)
u_int temp;
/*
+ * Install vectors
+ *
+ * Since IDT is shared between BSP and APs, these vectors
+ * only need to be installed once; we do it on BSP.
+ */
+ if (bsp) {
+ /* Install a 'Spurious INTerrupt' vector */
+ setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
+ SDT_SYSIGT, SEL_KPL, 0);
+
+ /* Install an inter-CPU IPI for TLB invalidation */
+ setidt(XINVLTLB_OFFSET, Xinvltlb,
+ SDT_SYSIGT, SEL_KPL, 0);
+
+ /* Install an inter-CPU IPI for IPIQ messaging */
+ setidt(XIPIQ_OFFSET, Xipiq,
+ SDT_SYSIGT, SEL_KPL, 0);
+
+ /* Install a timer vector */
+ setidt(XTIMER_OFFSET, Xtimer,
+ SDT_SYSIGT, SEL_KPL, 0);
+
+ /* Install an inter-CPU IPI for CPU stop/restart */
+ setidt(XCPUSTOP_OFFSET, Xcpustop,
+ SDT_SYSIGT, SEL_KPL, 0);
+ }
+
+ /*
* Setup LINT0 as ExtINT on the BSP. This is theoretically an
* aggregate interrupt input from the 8259. The INTA cycle
* will be routed to the external controller (the 8259) which
View
24 sys/platform/pc64/x86_64/mp_machdep.c
@@ -710,30 +710,6 @@ if (apic_io_enable && ioapic_use_old) {
}
- /*
- * These are required for SMP operation
- */
-
- /* install a 'Spurious INTerrupt' vector */
- setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
- SDT_SYSIGT, SEL_KPL, 0);
-
- /* install an inter-CPU IPI for TLB invalidation */
- setidt(XINVLTLB_OFFSET, Xinvltlb,
- SDT_SYSIGT, SEL_KPL, 0);
-
- /* install an inter-CPU IPI for IPIQ messaging */
- setidt(XIPIQ_OFFSET, Xipiq,
- SDT_SYSIGT, SEL_KPL, 0);
-
- /* install a timer vector */
- setidt(XTIMER_OFFSET, Xtimer,
- SDT_SYSIGT, SEL_KPL, 0);
-
- /* install an inter-CPU IPI for CPU stop/restart */
- setidt(XCPUSTOP_OFFSET, Xcpustop,
- SDT_SYSIGT, SEL_KPL, 0);
-
/* start each Application Processor */
start_all_aps(boot_addr);
}

0 comments on commit dbfb3a5

Please sign in to comment.
Something went wrong with that request. Please try again.