Simple MOS 6502 ALU Simulation in Verilog
This is the ALU for my own microprocessor design based on the MOS 6502. It is designed to run on a Xilinx Spartan 6 FPGA and it's written using Verilog. The project was created and simulated using the Xilinx ISE 14.7. This is part of an independent study project and the full documentation can be found on my website rangeli.net.