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Mailboxes facilitate communication between the ARM and the VideoCore. This page lists the available mailboxes/channels. Each mailbox is an 8-deep FIFO of 32-bit words, which can be read (popped)/written (pushed) by the ARM and VC. Only mailbox 0's status can trigger interrupts on the ARM, so MB 0 is always for communication from VC to ARM and MB 1 is for ARM to VC. The ARM should never write MB 0 or read MB 1.
The following lists the currently defined mailbox channels, with links to pages describing the format of the messages.
Mailbox 0 defines the following channels:
The following table shows the register offsets for the different mailboxes. For a description of the procedure for using these registers to access a mailbox, see here.
Mailbox Peek Read/Write Status Sender Config 0 0x10 0x00 0x18 0x14 0x1c 1 0x30 0x20 0x38 0x34 0x3c