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Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1…

…. Should give about 10% more ARM performance.

Thanks to Gordon and Costas
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popcornmix committed Aug 31, 2012
1 parent f0dbf1e commit f010d94155524454e2d5a9463ad6ca2b4fb81a2e
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@@ -1,4 +1,4 @@
-config ARM
+iconfig ARM
bool
default y
select ARCH_HAVE_CUSTOM_GPIO_H
@@ -1010,6 +1010,7 @@ config ARCH_BCM2708
select ARM_ERRATA_411920
select MACH_BCM2708
select VC4
+ select FIQ
help
This enables support for Broadcom BCM2708 boards.
@@ -42,6 +42,7 @@ extern void disable_fiq(int fiq);
/* helpers defined in fiqasm.S: */
extern void __set_fiq_regs(unsigned long const *regs);
extern void __get_fiq_regs(unsigned long *regs);
+extern void __FIQ_Branch(unsigned long *regs);
static inline void set_fiq_regs(struct pt_regs const *regs)
{
View
@@ -137,6 +137,7 @@ void disable_fiq(int fiq)
EXPORT_SYMBOL(set_fiq_handler);
EXPORT_SYMBOL(__set_fiq_regs); /* defined in fiqasm.S */
EXPORT_SYMBOL(__get_fiq_regs); /* defined in fiqasm.S */
+EXPORT_SYMBOL(__FIQ_Branch); /* defined in fiqasm.S */
EXPORT_SYMBOL(claim_fiq);
EXPORT_SYMBOL(release_fiq);
EXPORT_SYMBOL(enable_fiq);
View
@@ -47,3 +47,7 @@ ENTRY(__get_fiq_regs)
mov r0, r0 @ avoid hazard prior to ARMv4
mov pc, lr
ENDPROC(__get_fiq_regs)
+
+ENTRY(__FIQ_Branch)
+ mov pc, r8
+ENDPROC(__FIQ_Branch)
@@ -59,12 +59,20 @@ static void armctrl_mask_irq(unsigned int irq)
IO_ADDRESS(ARM_IRQ_DIBL3),
0
};
+
+ if(d->irq >= FIQ_START)
+ {
+ writel(0, __io(IO_ADDRESS(ARM_IRQ_FAST)));
+ }
+ else
+ {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
- unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
#else
- unsigned int data = (unsigned int)get_irq_chip_data(irq);
+ unsigned int data = (unsigned int)get_irq_chip_data(irq);
#endif
- writel(1 << (data & 0x1f), __io(disables[(data >> 5) & 0x3]));
+ writel(1 << (data & 0x1f), __io(disables[(data >> 5) & 0x3]));
+ }
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
@@ -79,12 +87,21 @@ static void armctrl_unmask_irq(unsigned int irq)
IO_ADDRESS(ARM_IRQ_ENBL3),
0
};
+
+ if(d->irq >= FIQ_START)
+ {
+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
+ writel(0x80 | data, __io(IO_ADDRESS(ARM_IRQ_FAST)));
+ }
+ else
+ {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
- unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
#else
- unsigned int data = (unsigned int)get_irq_chip_data(irq);
+ unsigned int data = (unsigned int)get_irq_chip_data(irq);
#endif
- writel(1 << (data & 0x1f), __io(enables[(data >> 5) & 0x3]));
+ writel(1 << (data & 0x1f), __io(enables[(data >> 5) & 0x3]));
+ }
}
#if defined(CONFIG_PM)
@@ -379,7 +396,7 @@ int __init armctrl_init(void __iomem * base, unsigned int irq_start,
for (irq = 0; irq < NR_IRQS; irq++) {
unsigned int data = irq;
- if (irq >= INTERRUPT_JPEG)
+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
data = remap_irqs[irq - INTERRUPT_JPEG];
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
@@ -349,12 +349,32 @@ static struct resource bcm2708_usb_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_USB,
- .end = IRQ_USB,
+ .start = MPHI_BASE,
+ .end = MPHI_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = IRQ_HOSTPORT,
+ .end = IRQ_HOSTPORT,
.flags = IORESOURCE_IRQ,
},
};
+extern bool fiq_fix_enable;
+
+static struct resource bcm2708_usb_resources_no_fiq_fix[] = {
+ [0] = {
+ .start = USB_BASE,
+ .end = USB_BASE + SZ_128K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB,
+ .end = IRQ_USB,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
static struct platform_device bcm2708_usb_device = {
@@ -617,6 +637,11 @@ void __init bcm2708_init(void)
bcm_register_device(&bcm2708_mci_device);
#endif
bcm_register_device(&bcm2708_fb_device);
+ if (!fiq_fix_enable)
+ {
+ bcm2708_usb_device.resource = bcm2708_usb_resources_no_fiq_fix;
+ bcm2708_usb_device.num_resources = ARRAY_SIZE(bcm2708_usb_resources_no_fiq_fix);
+ }
bcm_register_device(&bcm2708_usb_device);
bcm_register_device(&bcm2708_uart1_device);
bcm_register_device(&bcm2708_powerman_device);
@@ -106,91 +106,94 @@
#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
+#define FIQ_START HARD_IRQS
+
/*
* FIQ interrupts definitions are the same as the INT definitions.
*/
-#define FIQ_TIMER0 INT_TIMER0
-#define FIQ_TIMER1 INT_TIMER1
-#define FIQ_TIMER2 INT_TIMER2
-#define FIQ_TIMER3 INT_TIMER3
-#define FIQ_CODEC0 INT_CODEC0
-#define FIQ_CODEC1 INT_CODEC1
-#define FIQ_CODEC2 INT_CODEC2
-#define FIQ_JPEG INT_JPEG
-#define FIQ_ISP INT_ISP
-#define FIQ_USB INT_USB
-#define FIQ_3D INT_3D
-#define FIQ_TRANSPOSER INT_TRANSPOSER
-#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0
-#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1
-#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2
-#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3
-#define FIQ_DMA0 INT_DMA0
-#define FIQ_DMA1 INT_DMA1
-#define FIQ_DMA2 INT_DMA2
-#define FIQ_DMA3 INT_DMA3
-#define FIQ_DMA4 INT_DMA4
-#define FIQ_DMA5 INT_DMA5
-#define FIQ_DMA6 INT_DMA6
-#define FIQ_DMA7 INT_DMA7
-#define FIQ_DMA8 INT_DMA8
-#define FIQ_DMA9 INT_DMA9
-#define FIQ_DMA10 INT_DMA10
-#define FIQ_DMA11 INT_DMA11
-#define FIQ_DMA12 INT_DMA12
-#define FIQ_AUX INT_AUX
-#define FIQ_ARM INT_ARM
-#define FIQ_VPUDMA INT_VPUDMA
-#define FIQ_HOSTPORT INT_HOSTPORT
-#define FIQ_VIDEOSCALER INT_VIDEOSCALER
-#define FIQ_CCP2TX INT_CCP2TX
-#define FIQ_SDC INT_SDC
-#define FIQ_DSI0 INT_DSI0
-#define FIQ_AVE INT_AVE
-#define FIQ_CAM0 INT_CAM0
-#define FIQ_CAM1 INT_CAM1
-#define FIQ_HDMI0 INT_HDMI0
-#define FIQ_HDMI1 INT_HDMI1
-#define FIQ_PIXELVALVE1 INT_PIXELVALVE1
-#define FIQ_I2CSPISLV INT_I2CSPISLV
-#define FIQ_DSI1 INT_DSI1
-#define FIQ_PWA0 INT_PWA0
-#define FIQ_PWA1 INT_PWA1
-#define FIQ_CPR INT_CPR
-#define FIQ_SMI INT_SMI
-#define FIQ_GPIO0 INT_GPIO0
-#define FIQ_GPIO1 INT_GPIO1
-#define FIQ_GPIO2 INT_GPIO2
-#define FIQ_GPIO3 INT_GPIO3
-#define FIQ_I2C INT_I2C
-#define FIQ_SPI INT_SPI
-#define FIQ_I2SPCM INT_I2SPCM
-#define FIQ_SDIO INT_SDIO
-#define FIQ_UART INT_UART
-#define FIQ_SLIMBUS INT_SLIMBUS
-#define FIQ_VEC INT_VEC
-#define FIQ_CPG INT_CPG
-#define FIQ_RNG INT_RNG
-#define FIQ_ARASANSDIO INT_ARASANSDIO
-#define FIQ_AVSPMON INT_AVSPMON
+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
+#define FIQ_USB (FIQ_START+INTERRUPT_USB)
+#define FIQ_3D (FIQ_START+INTERRUPT_3D)
+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
+#define FIQ_UART (FIQ_START+INTERRUPT_UART)
+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
-#define FIQ_ARM_TIMER INT_ARM_TIMER
-#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX
-#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0
-#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1
-#define FIQ_VPU0_HALTED INT_VPU0_HALTED
-#define FIQ_VPU1_HALTED INT_VPU1_HALTED
-#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0
-#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1
-#define FIQ_PENDING1 INT_PENDING1
-#define FIQ_PENDING2 INT_PENDING2
+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
-#define HARD_IRQS (64 + 21)
-#define GPIO_IRQ_START HARD_IRQS
+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
-#define GPIO_IRQS 32*5
+#define HARD_IRQS (64 + 21)
+#define FIQ_IRQS (64 + 21)
+#define GPIO_IRQS (32*5)
-#define NR_IRQS HARD_IRQS+GPIO_IRQS
+#define NR_IRQS HARD_IRQS+FIQ_IRQS+GPIO_IRQS
#endif /* _BCM2708_IRQS_H_ */
@@ -56,7 +56,9 @@
*/
#define BCM2708_PERI_BASE 0x20000000
+#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
+#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
@@ -36,6 +36,7 @@ dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o
dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
dwc_otg-objs += dwc_otg_adp.o
+dwc_otg-objs += dwc_otg_mphi_fix.o
ifneq ($(CFI),)
dwc_otg-objs += dwc_otg_cfi.o
endif
@@ -45,6 +45,9 @@
#include "dwc_otg_driver.h"
#include "dwc_otg_pcd.h"
#include "dwc_otg_hcd.h"
+#include "dwc_otg_mphi_fix.h"
+
+extern bool fiq_fix_enable;
#ifdef DEBUG
inline const char *op_state_str(dwc_otg_core_if_t * core_if)
@@ -1351,10 +1354,15 @@ static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if)
gintsts.d32, gintmsk.d32);
}
#endif
- if (gahbcfg.b.glblintrmsk)
+ if (!fiq_fix_enable){
+ if (gahbcfg.b.glblintrmsk)
+ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
+ else
+ return 0;
+ }
+ else {
return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
- else
- return 0;
+ }
}
@@ -49,6 +49,7 @@ static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
return old;
}
+#define DBG_USER (0x1)
/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
#define DBG_CIL (0x2)
/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
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