From ec5b3cbd73e24ce0d60057346f690863ffbdd3d9 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 12 Nov 2025 08:51:20 +0000 Subject: [PATCH 1/3] mmc: bcm2835-mmc: Relax the 50MHz overclock check EMMC clock speeds are based around divisions of 52Mhz, not the 50MHz used by SD. As such, relax the "full speed" check (intended to stop any overclock whenever an operation has to be retried) so that any requested speed of 50MHz or higher will be overclocked. See: https://github.com/raspberrypi/linux/issues/7120 Signed-off-by: Phil Elwell --- drivers/mmc/host/bcm2835-mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/bcm2835-mmc.c b/drivers/mmc/host/bcm2835-mmc.c index e24e6bec329e08..dc889bbb7542c8 100644 --- a/drivers/mmc/host/bcm2835-mmc.c +++ b/drivers/mmc/host/bcm2835-mmc.c @@ -1068,7 +1068,7 @@ static void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock) unsigned long timeout; unsigned int input_clock = clock; - if (host->overclock_50 && (clock == 50000000)) + if (host->overclock_50 && (clock >= 50000000)) clock = host->overclock_50 * 1000000 + 999999; host->mmc->actual_clock = 0; From 37c5eecaf2da33b57ff7c130046007937896e61e Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 12 Nov 2025 09:00:02 +0000 Subject: [PATCH 2/3] mmc: bcm2835-sdhost: Relax 50MHz overclock check EMMC clock speeds are based around divisions of 52Mhz, not the 50MHz used by SD. As such, relax the "full speed" check (intended to stop any overclock whenever an operation has to be retried) so that any requested speed of 50MHz or higher will be overclocked. Signed-off-by: Phil Elwell --- drivers/mmc/host/bcm2835-sdhost.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/bcm2835-sdhost.c b/drivers/mmc/host/bcm2835-sdhost.c index f47d78f9668595..45e7ed7c0f85fa 100644 --- a/drivers/mmc/host/bcm2835-sdhost.c +++ b/drivers/mmc/host/bcm2835-sdhost.c @@ -1541,7 +1541,7 @@ static void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clo if (host->debug) pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock); - if (host->overclock_50 && (clock == 50*MHZ)) + if (host->overclock_50 && (clock >= 50*MHZ)) clock = host->overclock_50 * MHZ + (MHZ - 1); /* The SDCDIV register has 11 bits, and holds (div - 2). From be2406291395769bc73cd26891039b5402bae9d0 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 12 Nov 2025 14:12:57 +0000 Subject: [PATCH 3/3] mmc: bcm2835: Relax the 50MHz overclock check EMMC clock speeds are based around divisions of 52Mhz, not the 50MHz used by SD. As such, relax the "full speed" check (intended to stop any overclock whenever an operation has to be retried) so that any requested speed of 50MHz or higher will be overclocked. Signed-off-by: Phil Elwell --- drivers/mmc/host/bcm2835.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c index 318176720f06cc..a6ce4fd61c161e 100644 --- a/drivers/mmc/host/bcm2835.c +++ b/drivers/mmc/host/bcm2835.c @@ -1127,7 +1127,7 @@ static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) const unsigned int MHZ = 1000000; int div; - if (host->overclock_50 && (clock == 50*MHZ)) + if (host->overclock_50 && (clock >= 50*MHZ)) clock = host->overclock_50 * MHZ + (MHZ - 1); /* The SDCDIV register has 11 bits, and holds (div - 2). But