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armstub7: Various fixes #85

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@AntonioND

AntonioND commented Nov 7, 2017

Various fixes to armstub7.

Original message:

The previous code was enabling both I and D-caches, but keeping the
bit M as the reset value, which is architecturally undetermined. In
practice, in both Cortex-A7 and Cortex-A53, the reset value is 0, so
the D-cache was disabled (but the I-cache was enabled).

For the 32-bit Arm architecture boot, the Linux kernel expects the data
cache and MMU to be disabled when the CPU jumps into it, the I-cache
doesn't matter, as specified in the file Documentation/arm/Booting of
the Linux kernel tree under Calling the kernel image.

This patch disables the D-cache and MMU for correctness while keeping
the I-cache enabled to save a few cycles during the execution of the
stub.

Fixes #84

armstub7: Disable data cache and MMU
The previous code was enabling both I and D-caches, but keeping the
bit M as the reset value, which is architecturally undetermined. In
practice, in both Cortex-A7 and Cortex-A53, the reset value is 0, so
the D-cache was disabled (but the I-cache was enabled).

For the 32-bit Arm architecture boot, the Linux kernel expects the data
cache and MMU to be disabled when the CPU jumps into it, the I-cache
doesn't matter, as specified in the file `Documentation/arm/Booting` of
the Linux kernel tree under `Calling the kernel image`.

This patch disables the D-cache and MMU for correctness while keeping
the I-cache enabled to save a few cycles during the execution of the
stub.

Signed-off-by: Antonio Niño Díaz <antonio_nd@outlook.com>
@pelwell

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pelwell commented Nov 7, 2017

For other reviewers, see http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438i/BABJAHDA.html for details of the System Control Register.
That document says that both the D cache and MMU are disabled by default, which would suggest that the correct fix is to remove that line altogether, but since force_core mode relies on an instruction offset I'm happy for this to stay as it is.

@popcornmix?

@AntonioND

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AntonioND commented Nov 7, 2017

While it is true that for A7 and A53 both C and M bits are set to 0 on reset (according to their technical reference manuals), the ARM ARM says (at least, the ARMv8 ARM) When this register has an architecturally-defined reset value, this field resets to 0. so I don't think that explicitly disabling it is a bad idea in case it is needed by future models.

AntonioND added some commits Nov 22, 2017

armstub7: Set SMP before enabling instruction cache
According to the Technical Reference Manuals of both Cortex-A7 and
Cortex-A53, SMP must be enabled before enabling any caches.

Signed-off-by: Antonio Niño Díaz <antonio_nd@outlook.com>
armstub7: Fix reset NSACR values
In Cortex-A7, some reserved fields of NSACR were set to 1. According to
the Technical Reference Manual, the reserved fields of this register are
RAZ/WI (Read-As-Zero, Writes Ignored).

In Cortex-A53, all reserved fields are RES0. Software should respect
this for future compatibility.

The bits NS_SMP and NS_L2ERR of Cortex-A7 need to be set to 1 in order
for the Non-secure world to be able to modify the value of the SMP and
L2 AXI asynchronous error bits. However, in Cortex-A53 they are RES0.
This means that both CPUs can't share the same reset value.

Signed-off-by: Antonio Niño Díaz <antonio_nd@outlook.com>
armstub7: Remove useless initialization of CNTV_CTL
This register can be accessed from both user and privileged modes and it
is not used in the bootstrap, there is no reason to initialize it here.

Signed-off-by: Antonio Niño Díaz <antonio_nd@outlook.com>

@AntonioND AntonioND changed the title from armstub7: Disable data cache and MMU to armstub7: Various fixes Nov 22, 2017

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AntonioND commented Nov 22, 2017

I've added a couple of commits to fix other issues with this bootstrap (armstub7: Set SMP before enabling instruction cache and armstub7: Fix reset NSACR values).

I'm not sure about armstub7: Remove useless initialization of CNTV_CTL.

Note that I don't have a Raspberry Pi 2 to test the Cortex-A7 code.

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popcornmix commented Nov 22, 2017

The changes look quite reasonable. Will need double checking on Pi2/Pi3 and force_core firmware code may need patching, but otherwise seems fine.

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