diff --git a/BoardDisplay.vhd b/BoardDisplay.vhd
new file mode 100644
index 0000000..d33f220
--- /dev/null
+++ b/BoardDisplay.vhd
@@ -0,0 +1,105 @@
+----------------------------------------------------------------------------------
+--Code by: Zachary Rauen
+--Date: 10/6/14
+--Last Modified: 10/16/14
+--
+--Description: This is a 7 segment display that takes in
+-- a 16 bit number and displays it across 4 7 segment displays
+--
+--Version: 2.3
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity BoardDisplay is
+ Generic (RefreshRate : integer := 1000;
+ ClockSpeed : integer := 100000000);
+ Port ( ClockState : in std_logic;
+ Data : in std_logic_vector(15 downto 0);
+ DisplayVector : out std_logic_vector(7 downto 0);
+ SegmentVector : out std_logic_vector(7 downto 0));
+end BoardDisplay;
+
+architecture Behavioral of BoardDisplay is
+
+
+signal vectorSection : std_logic_vector(3 downto 0);
+signal segCnt : integer := 0;
+signal segCntMax : integer := 3;
+signal dispCarry : std_logic_vector(7 downto 0);
+signal SegmentEnable : std_logic;
+signal clkEnableMax : integer := ClockSpeed/RefreshRate;
+signal clkEnCnt : integer := 0;
+
+begin
+
+
+Refresh: process(ClockState)
+begin
+if rising_edge(ClockState) then
+ if clkEnCnt = clkEnableMax then
+ SegmentEnable <= '1';
+ clkEnCnt <= 0;
+ else
+ clkEnCnt<=clkEnCnt+1;
+ SegmentEnable <= '0';
+ end if;
+end if;
+if rising_edge(ClockState) AND SegmentEnable = '1' then
+ if segCnt = segCntMax then
+ segCnt <= 0;
+ else
+ segCnt <= segCnt + 1;
+ end if;
+end if;
+end process Refresh;
+
+Display: process(ClockState,Data)
+begin
+
+case segCnt is
+ when 0 =>
+ SegmentVector <="11111110";
+ vectorSection <=Data(3 downto 0);
+ when 1 =>
+ SegmentVector <="11111101";
+ vectorSection <=Data(7 downto 4);
+ when 2 =>
+ SegmentVector <="11111011";
+ vectorSection <=Data(11 downto 8);
+ when 3 =>
+ SegmentVector <="11110111";
+ vectorSection <=Data(15 downto 12);
+ when others =>
+ SegmentVector <="11111111";
+ vectorSection <="1111";
+end case;
+
+end process Display;
+with vectorSection select dispCarry <=
+ "11111100" when "0000",
+ "01100000" when "0001",
+ "11011010" when "0010",
+ "11110010" when "0011",
+ "01100110" when "0100",
+ "10110110" when "0101",
+ "10111110" when "0110",
+ "11100000" when "0111",
+ "11111110" when "1000",
+ "11110110" when "1001",
+ "11101110" when "1010",
+ "00111110" when "1011",
+ "10011100" when "1100",
+ "01111010" when "1101",
+ "10011110" when "1110",
+ "10001110" when "1111";
+
+DisplayVector<= NOT dispCarry;
+
+end Behavioral;
+
+
+
+
diff --git a/SPI_display.vhd b/SPI_display.vhd
new file mode 100644
index 0000000..1b7e042
--- /dev/null
+++ b/SPI_display.vhd
@@ -0,0 +1,189 @@
+----------------------------------------------------------------------------------
+--Code by: Zachary Rauen
+--Date: 10/30/14
+--Last Modified: 11/2/14
+--
+--Description: This takes in 16 bit data and displays them on an external display
+-- using GPIO and SPI communication.
+--
+--Version: 1.1
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity SPI_display is
+Generic (constant BoardClockSpeed : integer := 100000000;
+ constant SCKSpeed : integer := 250000);
+ Port ( BoardClock : in STD_LOGIC;
+ Data : in STD_LOGIC_VECTOR (15 downto 0);
+ SCK : out STD_LOGIC;
+ SS : out STD_LOGIC;
+ MOSI : out STD_LOGIC
+ );
+end SPI_display;
+
+architecture Behavioral of SPI_display is
+
+signal clkMax : integer := (BoardClockSpeed/SCKSpeed)-1;
+signal clkCnt : integer := 0;
+signal StateClock : std_logic :='0';
+type state_type is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9,
+state10,state11,state12,state13,state14,state15,state16,state17,state18);
+signal currentState : state_type :=state0;
+signal nextState : state_type;
+signal dataSection : std_logic_vector(7 downto 0);
+signal byteChoice: integer :=0;
+signal byteMax: integer :=8;
+begin
+
+ClkEnable : process(BoardClock)
+begin
+if rising_edge(BoardClock) then
+ if clkCnt = clkMax then
+ StateClock <= '1';
+ clkCnt <= 0;
+ else
+ clkCnt<=clkCnt+1;
+ StateClock <= '0';
+ end if;
+end if;
+end process ClkEnable;
+
+StateChange: process (BoardClock,StateClock)
+begin
+if (rising_edge(BoardClock) and StateClock='1') then
+if currentState = state18 then
+ if byteChoice = byteMax then
+ byteChoice <= byteChoice-3;
+ else
+ byteChoice<=byteChoice+1;
+ end if;
+end if;
+ currentState <= nextState;
+end if;
+
+end process StateChange;
+
+States: process(currentState)
+begin
+case currentState is
+ when state0=>
+ SCK<='0';
+ SS<='1';
+ MOSI<='Z';
+ nextState<=state1;
+ when state1=>
+ SCK<='0';
+ SS<='0';
+ MOSI<=dataSection(7);
+ nextState<=state2;
+ when state2=>
+ SCK<='1';
+ SS<='0';
+ MOSI<=dataSection(7);
+ nextState<=state3;
+ when state3=>
+ SCK<='0';
+ SS<='0';
+ MOSI<=dataSection(6);
+ nextState<=state4;
+ when state4=>
+ SCK<='1';
+ SS<='0';
+ MOSI<=dataSection(6);
+ nextState<=state5;
+ when state5=>
+ SCK<='0';
+ SS<='0';
+ MOSI<=dataSection(5);
+ nextState<=state6;
+ when state6=>
+ SCK<='1';
+ SS<='0';
+ MOSI<=dataSection(5);
+ nextState<=state7;
+ when state7=>
+ SCK<='0';
+ SS<='0';
+ MOSI<=dataSection(4);
+ nextState<=state8;
+ when state8=>
+ SCK<='1';
+ SS<='0';
+ MOSI<=dataSection(4);
+ nextState<=state9;
+ when state9=>
+ SCK<='0';
+ SS<='0';
+ MOSI<=dataSection(3);
+ nextState<=state10;
+ when state10=>
+ SCK<='1';
+ SS<='0';
+ MOSI<=dataSection(3);
+ nextState<=state11;
+ when state11=>
+ SCK<='0';
+ SS<='0';
+ MOSI<=dataSection(2);
+ nextState<=state12;
+ when state12=>
+ SCK<='1';
+ SS<='0';
+ MOSI<=dataSection(2);
+ nextState<=state13;
+ when state13=>
+ SCK<='0';
+ SS<='0';
+ MOSI<=dataSection(1);
+ nextState<=state14;
+ when state14=>
+ SCK<='1';
+ SS<='0';
+ MOSI<=dataSection(1);
+ nextState<=state15;
+ when state15=>
+ SCK<='0';
+ SS<='0';
+ MOSI<=dataSection(0);
+ nextState<=state16;
+ when state16=>
+ SCK<='1';
+ SS<='0';
+ MOSI<=dataSection(0);
+ nextState<=state17;
+ when state17=>
+ SCK<='0';
+ SS<='0';
+ MOSI<=datasection(0);
+ nextState<=state18;
+ when state18=>
+ SCK<='0';
+ SS<='1';
+ MOSI<='Z';
+ nextState<=state1;
+end case;
+
+end process States;
+
+ByteSelection: process(byteChoice)
+begin
+case byteChoice is
+ when 0 => dataSection<=x"76";
+ when 1 => dataSection<=x"76";
+ when 2 => dataSection<=x"76";
+ when 3 => dataSection<=x"76";
+ when 4 => dataSection<=x"76";
+ when 5 => dataSection <=x"0" & Data(15 downto 12);
+ when 6 => dataSection <=x"0" & Data(11 downto 8);
+ when 7 => dataSection <=x"0" & Data(7 downto 4);
+ when 8 => dataSection <=x"0" & Data(3 downto 0);
+ when others => dataSection <="11111111";
+end case;
+end process ByteSelection;
+
+
+end Behavioral;
+
diff --git a/SequenceController.vhd b/SequenceController.vhd
new file mode 100644
index 0000000..b3d9efb
--- /dev/null
+++ b/SequenceController.vhd
@@ -0,0 +1,87 @@
+----------------------------------------------------------------------------------
+--Code by: Zachary Rauen
+--Date: 10/6/14
+--Last Modified: 11/2/14
+--
+--Description: This is a sequence controller that uses three buttons as
+-- reset, reverse and a system enable. Using the clock this sytem will
+-- generate an address for a ROM. However, this can be easily
+-- modified in order to create what is needed
+--
+--Version: 2.1
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity SequenceController is
+ Generic (NumOfSequences : integer := 8;
+ DesiredDisplaySpeed : integer := 100000;
+ InputClockSpeed : integer := 100000000);
+ Port ( ClockState : in std_logic;
+ Enabler : in std_logic;
+ Reset : in std_logic;
+ Reverse : in std_logic;
+ MemAddress : out integer := 0);
+end SequenceController;
+
+architecture Behavioral of SequenceController is
+
+signal clkMax : integer := InputClockSpeed/DesiredDisplaySpeed;
+signal clkCnt : integer := 0;
+signal displayCnt : integer := 0;
+signal StateEnable : std_logic;
+
+
+
+begin
+
+DisplaySpeed: process(ClockState)
+begin
+if rising_edge(ClockState) then
+ if Reset <= '0' then
+ if clkCnt = clkMax then
+ StateEnable <= '1';
+ clkCnt <= 0;
+ else
+ clkCnt<=clkCnt+1;
+ StateEnable <= '0';
+ end if;
+ else
+ clkCnt<=0;
+ end if;
+end if;
+
+end process DisplaySpeed;
+
+
+count: process(ClockState,StateEnable,Enabler,Reverse,Reset)
+begin
+ if Reset='1' then
+ displayCnt <= 0;
+ else
+ if Enabler = '1' then
+ if rising_edge(ClockState) AND StateEnable = '1' then
+ if Reverse = '0' then
+ if displayCnt = NumOfSequences then
+ displayCnt <= 0;
+ else
+ displayCnt <= displayCnt + 1;
+ end if;
+ else
+ if displayCnt = 0 then
+ displayCnt <= NumOfSequences;
+ else
+ displayCnt <= displayCnt - 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+MemAddress<=displayCnt;
+
+end process count;
+
+
+end Behavioral;
diff --git a/Serial_TTL_Display.vhd b/Serial_TTL_Display.vhd
new file mode 100644
index 0000000..bcbe269
--- /dev/null
+++ b/Serial_TTL_Display.vhd
@@ -0,0 +1,127 @@
+----------------------------------------------------------------------------------
+--Code by: Zachary Rauen
+--Date: 10/28/14
+--Last Modified: 11/2/14
+--
+--Description: This takes in 16 bit data and displays them on an external display
+-- using GPIO and serial ttl communication.
+--
+--Version: 1.3
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity Serial_TTL_display is
+ Generic (BaudSpeed : integer :=9600;
+ Boardspeed : integer :=100000000);
+ Port ( Clock : in STD_LOGIC;
+ Data : in STD_LOGIC_VECTOR (15 downto 0);
+ RX : out STD_LOGIC);
+end Serial_TTL_display;
+
+architecture Behavioral of Serial_TTL_display is
+
+signal DataSection : std_logic_vector(7 downto 0);
+type state_type is (bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9);
+signal nextState : state_type;
+signal currentState : state_type := bit0;
+signal bitEnableCnt,ByteChoice : integer:=0;
+signal ByteMax : integer :=8;
+signal BitEnable : std_logic :='0';
+signal BaudClockEnableMax : integer := Boardspeed/BaudSpeed-1;
+
+begin
+
+BitEnabler: process(Clock)
+begin
+if rising_edge(Clock) then
+ if bitEnableCnt = BaudClockEnableMax then
+ BitEnable <= '1';
+ bitEnableCnt <= 0;
+ else
+ bitEnableCnt<=bitEnableCnt+1;
+ BitEnable <= '0';
+ end if;
+end if;
+end process BitEnabler;
+
+
+
+
+StateChange: process (Clock,BitEnable)
+begin
+if (rising_edge(Clock) and BitEnable='1') then
+ if currentState = bit9 then
+ if ByteChoice = ByteMax then
+ ByteChoice <= Bytechoice-3;
+ else
+ ByteChoice<=ByteChoice+1;
+ end if;
+ end if;
+
+ currentState <= nextState;
+end if;
+
+end process StateChange;
+
+
+
+States: process(currentState)
+begin
+case currentState is
+ when bit0=>
+ RX<='0';
+ nextState<=bit1;
+ when bit1=>
+ RX<=DataSection(0);
+ nextState<=bit2;
+ when bit2=>
+ RX<=DataSection(1);
+ nextState<=bit3;
+ when bit3=>
+ RX<=DataSection(2);
+ nextState<=bit4;
+ when bit4=>
+ RX<=DataSection(3);
+ nextState<=bit5;
+ when bit5=>
+ RX<=DataSection(4);
+ nextState<=bit6;
+ when bit6=>
+ RX<=DataSection(5);
+ nextState<=bit7;
+ when bit7=>
+ RX<=DataSection(6);
+ nextState<=bit8;
+ when bit8=>
+ RX<=DataSection(7);
+ nextState<=bit9;
+ when bit9=>
+ RX<='1';
+ nextState<=bit0;
+end case;
+
+
+
+case ByteChoice is
+ when 0 => DataSection<=x"76";
+ when 1 => DataSection<=x"76";
+ when 2 => DataSection<=x"76";
+ when 3 => DataSection<=x"76";
+ when 4 => DataSection<=x"76";
+-- when 5 => DataSection<=x"7A";
+-- when 6 => DataSection<=std_logic_vector(to_unsigned(0, 8));
+-- when 6 => DataSection<=x"79";
+-- when 7 => DataSection<=std_logic_vector(to_unsigned(0, 8));
+ when 5 => DataSection <=x"0" & Data(15 downto 12);
+ when 6 => DataSection <=x"0" & Data(11 downto 8);
+ when 7 => DataSection <=x"0" & Data(7 downto 4);
+ when 8 => DataSection <=x"0" & Data(3 downto 0);
+ when others => DataSection <="11111111";
+end case;
+end process States;
+
+end Behavioral;
diff --git a/btn_debounce_toggle.vhd b/btn_debounce_toggle.vhd
new file mode 100644
index 0000000..4d78fc5
--- /dev/null
+++ b/btn_debounce_toggle.vhd
@@ -0,0 +1,92 @@
+----------------------------------------------------------------------------
+-- btn_debounce.vhd -- Button Debouncer
+----------------------------------------------------------------------------
+-- Author: Sam Bobrowicz
+-- Copyright 2011 Digilent, Inc.
+-- Modified: Added toggle output
+----------------------------------------------------------------------------
+--
+----------------------------------------------------------------------------
+-- This component is used to debounce signals generated by external push
+-- buttons. It is designed to independently debounce a Push button signal.
+-- Debouncing is done by only registering a change in a button state if
+-- it remains constant for 2^16 clock cycles.
+--
+-- Port Descriptions:
+--
+-- BTN_I - The input button signals
+-- CLK - Behavior is optimized for a 100 MHz clock
+-- BTN_O - The debounced button signals
+-- TOGGLE_O - Debounced toggle output
+----------------------------------------------------------------------------
+--
+----------------------------------------------------------------------------
+-- Revision History:
+-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
+-- 10/06/2013 (CU): Converted to one button and added toggle output
+----------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_unsigned.all;
+
+entity btn_debounce_toggle is
+GENERIC (
+ CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF");
+ Port ( BTN_I : in STD_LOGIC;
+ CLK : in STD_LOGIC;
+ BTN_O : out STD_LOGIC;
+ TOGGLE_O : out STD_LOGIC);
+end btn_debounce_toggle;
+
+architecture Behavioral of btn_debounce_toggle is
+
+--constant CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF";
+signal btn_cntr : std_logic_vector(15 downto 0) := (others => '0');
+signal btn_reg : std_logic := '0';
+signal btn_toggle : std_logic := '1';
+signal btn_sync : std_logic_vector(1 downto 0) := (others => '0');
+signal btn_pulse : std_logic := '0';
+
+
+begin
+
+ btn_debounce_process : process (CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if (btn_cntr = CNTR_MAX) then
+ btn_reg <= not(btn_reg);
+ end if;
+ end if;
+ end process;
+
+ btn_counter_process : process (CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if ((btn_reg = '1') xor (BTN_I = '1')) then
+ if (btn_cntr = CNTR_MAX) then
+ btn_cntr <= (others => '0');
+ else
+ btn_cntr <= btn_cntr + 1;
+ end if;
+ else
+ btn_cntr <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+ btn_toggle_process : process(CLK)
+ begin
+ if (rising_edge(CLK)) then
+ btn_sync(0) <= btn_reg;
+ btn_sync(1) <= btn_sync(0);
+ btn_pulse <= not btn_sync(1) and btn_sync(0);
+ if btn_pulse = '1' then
+ btn_toggle <= not btn_toggle;
+ end if;
+ end if;
+ end process;
+
+ BTN_O <= btn_reg;
+ TOGGLE_O <= btn_toggle;
+
+end Behavioral;
\ No newline at end of file
diff --git a/i2c_controller.vhd b/i2c_controller.vhd
new file mode 100644
index 0000000..fecc7cd
--- /dev/null
+++ b/i2c_controller.vhd
@@ -0,0 +1,135 @@
+----------------------------------------------------------------------------------
+--Code by: Zachary Rauen
+--Date: 1/8/15
+--Last Modified: 1/15/15
+--
+--Description: This takes in 16 bit data and displays them on an external display
+-- using GPIO and I2C communication.
+--
+--Version: 2.1
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_unsigned.all;
+
+entity i2c_controller is
+ Generic (slave_addr : std_logic_vector(6 downto 0) := "1110001");
+ Port ( Clock : in STD_LOGIC;
+ dataIn : in STD_LOGIC_VECTOR (15 downto 0);
+ oSDA : inout STD_LOGIC;
+ oSCL : inout STD_LOGIC);
+end i2c_controller;
+
+architecture Behavioral of i2c_controller is
+
+component i2c_master IS
+ GENERIC(
+ input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz
+ bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
+ PORT(
+ clk : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --active low reset
+ ena : IN STD_LOGIC; --latch in command
+ addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
+ rw : IN STD_LOGIC; --'0' is write, '1' is read
+ data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
+ busy : OUT STD_LOGIC; --indicates transaction in progress
+ data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
+ ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
+ sda : INOUT STD_LOGIC; --serial data output of i2c bus
+ scl : INOUT STD_LOGIC); --serial clock output of i2c bus
+END component i2c_master;
+
+signal regBusy,sigBusy,reset,enable,readwrite,nack : std_logic;
+signal regData : std_logic_vector(15 downto 0);
+signal dataOut : std_logic_vector(7 downto 0);
+signal byteChoice : integer := 1;
+signal byteChoiceMax : integer := 13;
+signal initialCount : integer := 0;
+type state_type is (start,write,stop);
+signal State : state_type := start;
+signal address : std_logic_vector(6 downto 0);
+signal Cnt : integer := 16383;
+
+begin
+
+output: i2c_master
+port map (
+ clk=>Clock,
+ reset_n=>reset,
+ ena=>enable,
+ addr=>address,
+ rw=>readwrite,
+ data_wr=>dataOut,
+ busy=>sigBusy,
+ data_rd=>OPEN,
+ ack_error=>nack,
+ sda=>oSDA,
+ scl=>oSCL);
+
+
+StateChange: process (Clock)
+begin
+ if rising_edge(Clock) then
+ case State is
+ when start =>
+ if Cnt /= 0 then
+ Cnt<=Cnt-1;
+ reset<='0';
+ State<=start;
+ enable<='0';
+ else
+ reset<='1';
+ enable<='1';
+ address<=slave_addr;
+ readwrite<='0';
+ State<=write;
+ end if;
+
+ when write=>
+ regBusy<=sigBusy;
+ regData<=dataIn;
+ if regBusy/=sigBusy and sigBusy='0' then
+ if byteChoice /= byteChoiceMax then
+ byteChoice<=byteChoice+1;
+ State<=write;
+ else
+ byteChoice<=8;
+ State<=stop;
+ end if;
+ end if;
+
+ when stop=>
+ enable<='0';
+ if regData/=dataIn then
+ State<=start;
+ else
+ State<=stop;
+ end if;
+ end case;
+ end if;
+end process;
+
+process(byteChoice,Clock)
+begin
+ case byteChoice is
+ when 1 => dataOut <= x"76";
+ when 2 => dataOut <= x"76";
+ when 3 => dataOut <= x"76";
+ when 4 => dataOut <= x"7A";
+ when 5 => dataOut <= x"FF";
+ when 6 => dataOut <= x"77";
+ when 7 => dataOut <= x"00";
+ when 8 => dataOut <= x"79";
+ when 9 => dataOut <= x"00";
+ when 10 => dataOut <= x"0" & dataIn(15 downto 12);
+ when 11 => dataOut <= x"0" & dataIn(11 downto 8);
+ when 12 => dataOut <= x"0" & dataIn(7 downto 4);
+ when 13 => dataOut <= x"0" & dataIn(3 downto 0);
+ when others => dataOut <= x"76";
+ end case;
+end process;
+
+end Behavioral;
diff --git a/i2c_master.vhd b/i2c_master.vhd
new file mode 100644
index 0000000..cd4c97d
--- /dev/null
+++ b/i2c_master.vhd
@@ -0,0 +1,249 @@
+--------------------------------------------------------------------------------
+--
+-- FileName: i2c_master.vhd
+-- Dependencies: none
+-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
+--
+-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
+-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+-- Version History
+-- Version 1.0 11/1/2012 Scott Larson
+-- Initial Public Release
+-- Version 2.0 06/20/2014 Scott Larson
+-- Added ability to interface with different slaves in the same transaction
+-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
+-- Corrected timing of when ack_error signal clears
+-- Version 2.1 10/21/2014 Scott Larson
+-- Replaced gated clock with clock enable
+-- Adjusted timing of SCL during start and stop conditions
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY i2c_master IS
+ GENERIC(
+ input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz
+ bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
+ PORT(
+ clk : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --active low reset
+ ena : IN STD_LOGIC; --latch in command
+ addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
+ rw : IN STD_LOGIC; --'0' is write, '1' is read
+ data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
+ busy : OUT STD_LOGIC; --indicates transaction in progress
+ data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
+ ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
+ sda : INOUT STD_LOGIC; --serial data output of i2c bus
+ scl : INOUT STD_LOGIC); --serial clock output of i2c bus
+END i2c_master;
+
+ARCHITECTURE logic OF i2c_master IS
+ CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
+ TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
+ SIGNAL state : machine; --state machine
+ SIGNAL data_clk : STD_LOGIC; --data clock for sda
+ SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
+ SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
+ SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
+ SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
+ SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
+ SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
+ SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
+ SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
+ SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
+ SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
+ signal data_clk_m : std_logic;
+BEGIN
+
+ --generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
+ PROCESS(clk, reset_n)
+ VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
+ BEGIN
+ IF(reset_n = '0') THEN --reset asserted
+ stretch <= '0';
+ count := 0;
+ ELSIF(clk'EVENT AND clk = '1') THEN
+ data_clk_prev <= data_clk; --store previous value of data clock
+ IF(count = divider*4-1) THEN --end of timing cycle
+ count := 0; --reset timer
+ ELSIF(stretch = '0') THEN --clock stretching from slave not detected
+ count := count + 1; --continue clock generation timing
+ END IF;
+ CASE count IS
+ WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
+ scl_clk <= '0';
+ data_clk <= '0';
+ WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
+ scl_clk <= '0';
+ data_clk <= '1';
+ WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
+ scl_clk <= '1'; --release scl
+ IF(scl = '0') THEN --detect if slave is stretching clock
+ stretch <= '1';
+ ELSE
+ stretch <= '0';
+ END IF;
+ data_clk <= '1';
+ WHEN OTHERS => --last 1/4 cycle of clocking
+ scl_clk <= '1';
+ data_clk <= '0';
+ END CASE;
+ END IF;
+ END PROCESS;
+
+ --state machine and writing to sda during scl low (data_clk rising edge)
+ PROCESS(clk, reset_n)
+ BEGIN
+ IF(reset_n = '0') THEN --reset asserted
+ state <= ready; --return to initial state
+ busy <= '1'; --indicate not available
+ scl_ena <= '0'; --sets scl high impedance
+ sda_int <= '1'; --sets sda high impedance
+ ack_error <= '0'; --clear acknowledge error flag
+ bit_cnt <= 7; --restarts data bit counter
+ data_rd <= "00000000"; --clear data read port
+ ELSIF(clk'EVENT AND clk = '1') THEN
+ IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
+ CASE state IS
+ WHEN ready => --idle state
+ IF(ena = '1') THEN --transaction requested
+ busy <= '1'; --flag busy
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ state <= start; --go to start bit
+ ELSE --remain idle
+ busy <= '0'; --unflag busy
+ state <= ready; --remain idle
+ END IF;
+ WHEN start => --start bit of transaction
+ busy <= '1'; --resume busy if continuous mode
+ sda_int <= addr_rw(bit_cnt); --set first address bit to bus
+ state <= command; --go to command
+ WHEN command => --address and command byte of transaction
+ IF(bit_cnt = 0) THEN --command transmit finished
+ sda_int <= '1'; --release sda for slave acknowledge
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ state <= slv_ack1; --go to slave acknowledge (command)
+ ELSE --next clock cycle of command state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
+ state <= command; --continue with command
+ END IF;
+ WHEN slv_ack1 => --slave acknowledge bit (command)
+ IF(addr_rw(0) = '0') THEN --write command
+ sda_int <= data_tx(bit_cnt); --write first bit of data
+ state <= wr; --go to write byte
+ ELSE --read command
+ sda_int <= '1'; --release sda from incoming data
+ state <= rd; --go to read byte
+ END IF;
+ WHEN wr => --write byte of transaction
+ busy <= '1'; --resume busy if continuous mode
+ IF(bit_cnt = 0) THEN --write byte transmit finished
+ sda_int <= '1'; --release sda for slave acknowledge
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ busy<='0'; --modified
+ state <= slv_ack2; --go to slave acknowledge (write)
+ ELSE --next clock cycle of write state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ sda_int <= data_tx(bit_cnt-1); --write next bit to bus
+ state <= wr; --continue writing
+ END IF;
+ WHEN rd => --read byte of transaction
+ busy <= '1'; --resume busy if continuous mode
+ IF(bit_cnt = 0) THEN --read byte receive finished
+ IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
+ sda_int <= '0'; --acknowledge the byte has been received
+ ELSE --stopping or continuing with a write
+ sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
+ END IF;
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ data_rd <= data_rx; --output received data
+ state <= mstr_ack; --go to master acknowledge
+ ELSE --next clock cycle of read state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ state <= rd; --continue reading
+ END IF;
+ WHEN slv_ack2 => --slave acknowledge bit (write)
+ IF(ena = '1') THEN --continue transaction
+ -- busy <= '0'; --continue is accepted
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ IF(addr_rw = addr & rw) THEN --continue transaction with another write
+ busy <= '1';
+ sda_int <= data_wr(bit_cnt); --write first bit of data
+ state <= wr; --go to write byte
+ ELSE --continue transaction with a read or new slave
+ state <= start; --go to repeated start
+ END IF;
+ ELSE --complete transaction
+ state <= stop; --go to stop bit
+ END IF;
+ WHEN mstr_ack => --master acknowledge bit after a read
+ IF(ena = '1') THEN --continue transaction
+ busy <= '0'; --continue is accepted and data received is available on bus
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ IF(addr_rw = addr & rw) THEN --continue transaction with another read
+ sda_int <= '1'; --release sda from incoming data
+ state <= rd; --go to read byte
+ ELSE --continue transaction with a write or new slave
+ state <= start; --repeated start
+ END IF;
+ ELSE --complete transaction
+ state <= stop; --go to stop bit
+ END IF;
+ WHEN stop => --stop bit of transaction
+ busy <= '0'; --unflag busy
+ state <= ready; --go to idle state
+ END CASE;
+ ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
+ CASE state IS
+ WHEN start =>
+ IF(scl_ena = '0') THEN --starting new transaction
+ scl_ena <= '1'; --enable scl output
+ ack_error <= '0'; --reset acknowledge error output
+ END IF;
+ WHEN slv_ack1 => --receiving slave acknowledge (command)
+ IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
+ ack_error <= '1'; --set error output if no-acknowledge
+ END IF;
+ WHEN rd => --receiving slave data
+ data_rx(bit_cnt) <= sda; --receive current slave data bit
+ WHEN slv_ack2 => --receiving slave acknowledge (write)
+ IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
+ ack_error <= '1'; --set error output if no-acknowledge
+ END IF;
+ WHEN stop =>
+ scl_ena <= '0'; --disable scl
+ WHEN OTHERS =>
+ NULL;
+ END CASE;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ --set sda output
+ data_clk_m<=data_clk_prev and data_clk;
+ WITH state SELECT
+ sda_ena_n <= data_clk WHEN start, --generate start condition
+ NOT data_clk_m WHEN stop, --generate stop condition
+ sda_int WHEN OTHERS; --set to internal sda signal
+
+ --set scl and sda outputs
+ scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
+ sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
+
+END logic;
\ No newline at end of file
diff --git a/ip/SequenceStorage/SequenceStorage.dcp b/ip/SequenceStorage/SequenceStorage.dcp
new file mode 100644
index 0000000..0a18c29
Binary files /dev/null and b/ip/SequenceStorage/SequenceStorage.dcp differ
diff --git a/ip/SequenceStorage/SequenceStorage.mif b/ip/SequenceStorage/SequenceStorage.mif
new file mode 100644
index 0000000..7fc77ed
--- /dev/null
+++ b/ip/SequenceStorage/SequenceStorage.mif
@@ -0,0 +1,9 @@
+0000000000000000
+0000101000001010
+0101000001010000
+1111111001000101
+1010101010111011
+1100110011011101
+1111111011101101
+1101111010101101
+1011111011101111
diff --git a/ip/SequenceStorage/SequenceStorage.vho b/ip/SequenceStorage/SequenceStorage.vho
new file mode 100644
index 0000000..b0dabb9
--- /dev/null
+++ b/ip/SequenceStorage/SequenceStorage.vho
@@ -0,0 +1,79 @@
+-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
+-- IP Revision: 3
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT SequenceStorage
+ PORT (
+ clka : IN STD_LOGIC;
+ addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : SequenceStorage
+ PORT MAP (
+ clka => clka,
+ addra => addra,
+ douta => douta
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file SequenceStorage.vhd when simulating
+-- the core, SequenceStorage. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/ip/SequenceStorage/SequenceStorage.xci b/ip/SequenceStorage/SequenceStorage.xci
new file mode 100644
index 0000000..3bb8383
--- /dev/null
+++ b/ip/SequenceStorage/SequenceStorage.xci
@@ -0,0 +1,164 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ SequenceStorage
+
+
+ SequenceStorage
+ Native
+ AXI4_Full
+ Memory_Slave
+ false
+ 4
+ Single_Port_ROM
+ false
+ No_ECC
+ false
+ false
+ false
+ false
+ false
+ Single_Bit_Error_Injection
+ false
+ 9
+ Minimum_Area
+ 8kx2
+ false
+ 16
+ 9
+ 16
+ WRITE_FIRST
+ Always_Enabled
+ 16
+ 16
+ WRITE_FIRST
+ Always_Enabled
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 0
+ true
+ ..\..\imports\Vivado\intialization.coe
+ false
+ 0
+ false
+ false
+ CE
+ 0
+ false
+ false
+ CE
+ 0
+ SYNC
+ false
+ 100
+ 0
+ 0
+ 0
+ 100
+ 0
+ ALL
+ false
+ false
+ Stand_Alone
+ no_mem_loaded
+ NONE
+ artix7
+ artix7
+ ./
+ 0
+ 1
+ 0
+ 0
+ 0
+ NONE
+ 0
+ 4
+ 3
+ 9
+ 1
+ 1
+ 1
+ SequenceStorage.mif
+ SequenceStorage.mem
+ 0
+ 0
+ 0
+ CE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ WRITE_FIRST
+ 16
+ 16
+ 9
+ 9
+ 4
+ 0
+ CE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ WRITE_FIRST
+ 16
+ 16
+ 9
+ 9
+ 4
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ALL
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ Estimated Power for IP : 2.7096 mW
+ artix7
+ xc7a100t
+ csg324
+ -1
+ C
+
+ VHDL
+ MIXED
+ TRUE
+ TRUE
+
+ TRUE
+ 2014.4
+ 3
+ OUT_OF_CONTEXT
+
+ .
+ .
+
+
+
+
diff --git a/ip/SequenceStorage/SequenceStorage.xml b/ip/SequenceStorage/SequenceStorage.xml
new file mode 100644
index 0000000..494a62a
--- /dev/null
+++ b/ip/SequenceStorage/SequenceStorage.xml
@@ -0,0 +1,3700 @@
+
+
+ xilinx.com
+ customized_ip
+ SequenceStorage
+ 1.0
+
+
+ CLK.ACLK
+ ACLK
+ AXI4 Interconnect Clock Input
+
+
+
+
+
+
+ CLK
+
+
+ s_aclk
+
+
+
+
+
+ ASSOCIATED_BUSIF
+ AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI
+
+
+ ASSOCIATED_RESET
+ s_aresetn
+
+
+
+
+ RST.ARESETN
+ ARESETN
+ AXI4 Interconnect Reset Input
+
+
+
+
+
+
+ RST
+
+
+ s_aresetn
+
+
+
+
+
+ POLARITY
+ ACTIVE_LOW
+
+
+
+
+ AXI_SLAVE_S_AXI
+ AXI_SLAVE
+ AXI_SLAVE
+
+
+
+
+
+
+ ARADDR
+
+
+ s_axi_araddr
+
+
+
+
+ ARBURST
+
+
+ s_axi_arburst
+
+
+
+
+ ARID
+
+
+ s_axi_arid
+
+
+
+
+ ARLEN
+
+
+ s_axi_arlen
+
+
+
+
+ ARREADY
+
+
+ s_axi_arready
+
+
+
+
+ ARSIZE
+
+
+ s_axi_arsize
+
+
+
+
+ ARVALID
+
+
+ s_axi_arvalid
+
+
+
+
+ AWADDR
+
+
+ s_axi_awaddr
+
+
+
+
+ AWBURST
+
+
+ s_axi_awburst
+
+
+
+
+ AWID
+
+
+ s_axi_awid
+
+
+
+
+ AWLEN
+
+
+ s_axi_awlen
+
+
+
+
+ AWREADY
+
+
+ s_axi_awready
+
+
+
+
+ AWSIZE
+
+
+ s_axi_awsize
+
+
+
+
+ AWVALID
+
+
+ s_axi_awvalid
+
+
+
+
+ BID
+
+
+ s_axi_bid
+
+
+
+
+ BREADY
+
+
+ s_axi_bready
+
+
+
+
+ BRESP
+
+
+ s_axi_bresp
+
+
+
+
+ BVALID
+
+
+ s_axi_bvalid
+
+
+
+
+ RDATA
+
+
+ s_axi_rdata
+
+
+
+
+ RID
+
+
+ s_axi_rid
+
+
+
+
+ RLAST
+
+
+ s_axi_rlast
+
+
+
+
+ RREADY
+
+
+ s_axi_rready
+
+
+
+
+ RRESP
+
+
+ s_axi_rresp
+
+
+
+
+ RVALID
+
+
+ s_axi_rvalid
+
+
+
+
+ WDATA
+
+
+ s_axi_wdata
+
+
+
+
+ WLAST
+
+
+ s_axi_wlast
+
+
+
+
+ WREADY
+
+
+ s_axi_wready
+
+
+
+
+ WSTRB
+
+
+ s_axi_wstrb
+
+
+
+
+ WVALID
+
+
+ s_axi_wvalid
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ AXILite_SLAVE_S_AXI
+ AXILite_SLAVE
+ AXILite_SLAVE
+
+
+
+
+
+
+ ARADDR
+
+
+ s_axi_araddr
+
+
+
+
+ ARBURST
+
+
+ s_axi_arburst
+
+
+
+
+ ARID
+
+
+ s_axi_arid
+
+
+
+
+ ARLEN
+
+
+ s_axi_arlen
+
+
+
+
+ ARREADY
+
+
+ s_axi_arready
+
+
+
+
+ ARSIZE
+
+
+ s_axi_arsize
+
+
+
+
+ ARVALID
+
+
+ s_axi_arvalid
+
+
+
+
+ AWADDR
+
+
+ s_axi_awaddr
+
+
+
+
+ AWBURST
+
+
+ s_axi_awburst
+
+
+
+
+ AWID
+
+
+ s_axi_awid
+
+
+
+
+ AWLEN
+
+
+ s_axi_awlen
+
+
+
+
+ AWREADY
+
+
+ s_axi_awready
+
+
+
+
+ AWSIZE
+
+
+ s_axi_awsize
+
+
+
+
+ AWVALID
+
+
+ s_axi_awvalid
+
+
+
+
+ BID
+
+
+ s_axi_bid
+
+
+
+
+ BREADY
+
+
+ s_axi_bready
+
+
+
+
+ BRESP
+
+
+ s_axi_bresp
+
+
+
+
+ BVALID
+
+
+ s_axi_bvalid
+
+
+
+
+ RDATA
+
+
+ s_axi_rdata
+
+
+
+
+ RID
+
+
+ s_axi_rid
+
+
+
+
+ RLAST
+
+
+ s_axi_rlast
+
+
+
+
+ RREADY
+
+
+ s_axi_rready
+
+
+
+
+ RRESP
+
+
+ s_axi_rresp
+
+
+
+
+ RVALID
+
+
+ s_axi_rvalid
+
+
+
+
+ WDATA
+
+
+ s_axi_wdata
+
+
+
+
+ WLAST
+
+
+ s_axi_wlast
+
+
+
+
+ WREADY
+
+
+ s_axi_wready
+
+
+
+
+ WSTRB
+
+
+ s_axi_wstrb
+
+
+
+
+ WVALID
+
+
+ s_axi_wvalid
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ BRAM_PORTA
+ BRAM_PORTA
+ BRAM_PORTA
+
+
+
+
+
+
+ ADDR
+
+
+ addra
+
+
+
+
+ CLK
+
+
+ clka
+
+
+
+
+ DIN
+
+
+ dina
+
+
+
+
+ DOUT
+
+
+ douta
+
+
+
+
+ EN
+
+
+ ena
+
+
+
+
+ RST
+
+
+ rsta
+
+
+
+
+ WE
+
+
+ wea
+
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+ BRAM_PORTB
+ BRAM_PORTB
+ BRAM_PORTB
+
+
+
+
+
+
+ ADDR
+
+
+ addrb
+
+
+
+
+ CLK
+
+
+ clkb
+
+
+
+
+ DIN
+
+
+ dinb
+
+
+
+
+ DOUT
+
+
+ doutb
+
+
+
+
+ EN
+
+
+ enb
+
+
+
+
+ RST
+
+
+ rstb
+
+
+
+
+ WE
+
+
+ web
+
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+
+
+ S_1
+
+ Mem0
+ 0
+ 4096
+ 32
+ memory
+ read-write
+
+
+ OFFSET_BASE_PARAM
+ C_BASEADDR
+
+
+ OFFSET_HIGH_PARAM
+ C_HIGHADDR
+
+
+
+
+
+
+
+
+ xilinx_vhdlinstantiationtemplate
+ VHDL Instantiation Template
+ vhdlSource:vivado.xilinx.com:synthesis.template
+ vhdl
+
+ xilinx_vhdlinstantiationtemplate_view_fileset
+
+
+
+ customizationCRC
+ 7edd8d5d
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Tue Jan 20 16:02:05 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_miscfiles
+ Miscellaneous
+ :vivado.xilinx.com:misc.files
+
+ xilinx_miscfiles_view_fileset
+
+
+
+ customizationCRC
+ 7edd8d5d
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Tue Jan 20 16:02:10 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_versioninformation
+ Version Information
+ :vivado.xilinx.com:docs.versioninfo
+
+ xilinx_versioninformation_view_fileset
+
+
+
+ customizationCRC
+ 7edd8d5d
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Tue Jan 20 16:02:10 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_vhdlbehavioralsimulation
+ VHDL Simulation
+ vhdlSource:vivado.xilinx.com:simulation
+ vhdl
+ blk_mem_gen_v8_2
+
+ xilinx_vhdlbehavioralsimulation_view_fileset
+
+
+
+ customizationCRC
+ e0558b23
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Wed Jan 21 15:16:58 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_vhdlsimulationwrapper
+ VHDL Simulation Wrapper
+ vhdlSource:vivado.xilinx.com:simulation.wrapper
+ vhdl
+
+ xilinx_vhdlsimulationwrapper_view_fileset
+
+
+
+ customizationCRC
+ e0558b23
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Wed Jan 21 15:16:59 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_vhdlsynthesis
+ VHDL Synthesis
+ vhdlSource:vivado.xilinx.com:synthesis
+ vhdl
+
+ xilinx_vhdlsynthesis_view_fileset
+
+
+
+ customizationCRC
+ f9f02d0f
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Wed Jan 21 21:01:18 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_vhdlsynthesiswrapper
+ VHDL Synthesis Wrapper
+ vhdlSource:vivado.xilinx.com:synthesis.wrapper
+ vhdl
+
+ xilinx_vhdlsynthesiswrapper_view_fileset
+
+
+
+ customizationCRC
+ f9f02d0f
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Wed Jan 21 21:01:18 UTC 2015
+
+
+ StaleAtRelink
+ false
+
+
+
+
+ xilinx_externalfiles
+ External Files
+ :vivado.xilinx.com:external.files
+
+ xilinx_externalfiles_view_fileset
+
+
+
+ customizationCRC
+ f9f02d0f
+
+
+ customizationCRCversion
+ 4
+
+
+ GENtimestamp
+ Thu Jan 01 00:00:00 UTC 1970
+
+
+ StaleAtRelink
+ false
+
+
+
+
+
+
+ clka
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+ rsta
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ ena
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ regcea
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ wea
+
+ in
+
+ 0
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ addra
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+ dina
+
+ in
+
+ 15
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ douta
+
+ out
+
+ 15
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ true
+
+
+
+
+
+ clkb
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ rstb
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ enb
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ regceb
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ web
+
+ in
+
+ 0
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ addrb
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ dinb
+
+ in
+
+ 15
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ doutb
+
+ out
+
+ 15
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ injectsbiterr
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ injectdbiterr
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ eccpipece
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ sbiterr
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ dbiterr
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ rdaddrecc
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ sleep
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_aclk
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0x0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_aresetn
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_awid
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_awaddr
+
+ in
+
+ 31
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_awlen
+
+ in
+
+ 7
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_awsize
+
+ in
+
+ 2
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_awburst
+
+ in
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_awvalid
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_awready
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_wdata
+
+ in
+
+ 15
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_wstrb
+
+ in
+
+ 0
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_wlast
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_wvalid
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_wready
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_bid
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_bresp
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_bvalid
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_bready
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_arid
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_araddr
+
+ in
+
+ 31
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_arlen
+
+ in
+
+ 7
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_arsize
+
+ in
+
+ 2
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_arburst
+
+ in
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_arvalid
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_arready
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_rid
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_rdata
+
+ out
+
+ 15
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_rresp
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_rlast
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_rvalid
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_rready
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_injectsbiterr
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_injectdbiterr
+
+ in
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_sbiterr
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_dbiterr
+
+ out
+
+
+ std_logic
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+ s_axi_rdaddrecc
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_vhdlsynthesis
+ xilinx_vhdlbehavioralsimulation
+
+
+
+
+
+
+ optional
+ false
+
+
+
+
+
+
+
+ C_FAMILY
+ artix7
+
+
+ C_XDEVICEFAMILY
+ artix7
+
+
+ C_ELABORATION_DIR
+ ./
+
+
+ C_INTERFACE_TYPE
+ 0
+
+
+ C_AXI_TYPE
+ 1
+
+
+ C_AXI_SLAVE_TYPE
+ 0
+
+
+ C_USE_BRAM_BLOCK
+ 0
+
+
+ C_ENABLE_32BIT_ADDRESS
+ 0
+
+
+ C_CTRL_ECC_ALGO
+ NONE
+
+
+ C_HAS_AXI_ID
+ 0
+
+
+ C_AXI_ID_WIDTH
+ 4
+
+
+ C_MEM_TYPE
+ 3
+
+
+ C_BYTE_SIZE
+ 9
+
+
+ C_ALGORITHM
+ 1
+
+
+ C_PRIM_TYPE
+ 1
+
+
+ C_LOAD_INIT_FILE
+ 1
+
+
+ C_INIT_FILE_NAME
+ SequenceStorage.mif
+
+
+ C_INIT_FILE
+ SequenceStorage.mem
+
+
+ C_USE_DEFAULT_DATA
+ 0
+
+
+ C_DEFAULT_DATA
+ 0
+
+
+ C_HAS_RSTA
+ 0
+
+
+ C_RST_PRIORITY_A
+ CE
+
+
+ C_RSTRAM_A
+ 0
+
+
+ C_INITA_VAL
+ 0
+
+
+ C_HAS_ENA
+ 0
+
+
+ C_HAS_REGCEA
+ 0
+
+
+ C_USE_BYTE_WEA
+ 0
+
+
+ C_WEA_WIDTH
+ 1
+
+
+ C_WRITE_MODE_A
+ WRITE_FIRST
+
+
+ C_WRITE_WIDTH_A
+ 16
+
+
+ C_READ_WIDTH_A
+ 16
+
+
+ C_WRITE_DEPTH_A
+ 9
+
+
+ C_READ_DEPTH_A
+ 9
+
+
+ C_ADDRA_WIDTH
+ 4
+
+
+ C_HAS_RSTB
+ 0
+
+
+ C_RST_PRIORITY_B
+ CE
+
+
+ C_RSTRAM_B
+ 0
+
+
+ C_INITB_VAL
+ 0
+
+
+ C_HAS_ENB
+ 0
+
+
+ C_HAS_REGCEB
+ 0
+
+
+ C_USE_BYTE_WEB
+ 0
+
+
+ C_WEB_WIDTH
+ 1
+
+
+ C_WRITE_MODE_B
+ WRITE_FIRST
+
+
+ C_WRITE_WIDTH_B
+ 16
+
+
+ C_READ_WIDTH_B
+ 16
+
+
+ C_WRITE_DEPTH_B
+ 9
+
+
+ C_READ_DEPTH_B
+ 9
+
+
+ C_ADDRB_WIDTH
+ 4
+
+
+ C_HAS_MEM_OUTPUT_REGS_A
+ 1
+
+
+ C_HAS_MEM_OUTPUT_REGS_B
+ 0
+
+
+ C_HAS_MUX_OUTPUT_REGS_A
+ 0
+
+
+ C_HAS_MUX_OUTPUT_REGS_B
+ 0
+
+
+ C_MUX_PIPELINE_STAGES
+ 0
+
+
+ C_HAS_SOFTECC_INPUT_REGS_A
+ 0
+
+
+ C_HAS_SOFTECC_OUTPUT_REGS_B
+ 0
+
+
+ C_USE_SOFTECC
+ 0
+
+
+ C_USE_ECC
+ 0
+
+
+ C_EN_ECC_PIPE
+ 0
+
+
+ C_HAS_INJECTERR
+ 0
+
+
+ C_SIM_COLLISION_CHECK
+ ALL
+
+
+ C_COMMON_CLK
+ 0
+
+
+ C_DISABLE_WARN_BHV_COLL
+ 0
+
+
+ C_EN_SLEEP_PIN
+ 0
+
+
+ C_DISABLE_WARN_BHV_RANGE
+ 0
+
+
+ C_COUNT_36K_BRAM
+ 0
+
+
+ C_COUNT_18K_BRAM
+ 1
+
+
+ C_EST_POWER_SUMMARY
+ Estimated Power for IP : 2.7096 mW
+
+
+
+
+
+ choices_0
+ Native
+ AXI4
+
+
+ choices_1
+ AXI4_Full
+ AXI4_Lite
+
+
+ choices_2
+ Memory_Slave
+ Peripheral_Slave
+
+
+ choices_3
+ Single_Port_RAM
+ Simple_Dual_Port_RAM
+ True_Dual_Port_RAM
+ Single_Port_ROM
+ Dual_Port_ROM
+
+
+ choices_4
+ No_ECC
+ Soft_ECC
+ BuiltIn_ECC
+
+
+ choices_5
+ Single_Bit_Error_Injection
+ Double_Bit_Error_Injection
+ Single_and_Double_Bit_Error_Injection
+
+
+ choices_6
+ 8
+ 9
+
+
+ choices_7
+ Minimum_Area
+ Low_Power
+ Fixed_Primitives
+
+
+ choices_8
+ 16kx1
+ 8kx2
+ 4kx4
+ 2kx9
+ 1kx18
+ 512x36
+ 256x72
+
+
+ choices_9
+ 1
+ 2
+ 4
+ 8
+ 16
+
+
+ choices_10
+ WRITE_FIRST
+ READ_FIRST
+ NO_CHANGE
+
+
+ choices_11
+ Always_Enabled
+ Use_ENA_Pin
+
+
+ choices_12
+ 1
+ 2
+ 4
+ 8
+ 16
+
+
+ choices_13
+ 1
+ 2
+ 4
+ 8
+ 16
+
+
+ choices_14
+ WRITE_FIRST
+ READ_FIRST
+ NO_CHANGE
+
+
+ choices_15
+ Always_Enabled
+ Use_ENB_Pin
+
+
+ choices_16
+ 0
+ 1
+ 2
+ 3
+
+
+ choices_17
+ CE
+ SR
+
+
+ choices_18
+ CE
+ SR
+
+
+ choices_19
+ SYNC
+ ASYNC
+
+
+ choices_20
+ ALL
+ NONE
+ WARNING_ONLY
+ GENERATE_X_ONLY
+
+
+ choices_21
+ Stand_Alone
+ BRAM_Controller
+
+
+ choices_22
+ NONE
+ ECCH32-7
+ ECCH64-8
+ ECCHSIAO32-7
+ ECCHSIAO64-8
+ ECCHSIAO128-9
+
+
+
+
+ xilinx_vhdlinstantiationtemplate_view_fileset
+
+ SequenceStorage.vho
+ vhdlTemplate
+
+
+
+ xilinx_miscfiles_view_fileset
+
+ summary.log
+ log
+
+
+
+ xilinx_versioninformation_view_fileset
+
+ doc/blk_mem_gen_v8_2_changelog.txt
+ text
+
+
+
+ xilinx_vhdlbehavioralsimulation_view_fileset
+
+ SequenceStorage.mif
+ mif
+
+
+ blk_mem_gen_v8_2/simulation/blk_mem_gen_v8_2.vhd
+ vhdlSource
+ blk_mem_gen_v8_2
+ blk_mem_gen_v8_2
+
+
+
+ xilinx_vhdlsimulationwrapper_view_fileset
+
+ sim/SequenceStorage.vhd
+ vhdlSource
+ xil_defaultlib
+
+
+
+ xilinx_vhdlsynthesis_view_fileset
+
+ SequenceStorage_ooc.xdc
+ xdc
+ USED_IN_out_of_context
+ USED_IN_synthesis
+ USED_IN_implementation
+
+
+ blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_vhsyn_rfs.vhd
+ vhdlSource
+ blk_mem_gen_v8_2
+
+
+ blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
+ vhdlSource
+ blk_mem_gen_v8_2
+
+
+ SequenceStorage.mif
+ mif
+
+
+
+ xilinx_vhdlsynthesiswrapper_view_fileset
+
+ synth/SequenceStorage.vhd
+ vhdlSource
+ xil_defaultlib
+
+
+
+ xilinx_externalfiles_view_fileset
+
+ SequenceStorage.dcp
+ dcp
+ USED_IN_synthesis
+ USED_IN_implementation
+ xil_defaultlib
+
+
+ SequenceStorage_stub.v
+ verilogSource
+ USED_IN_synth_blackbox_stub
+ xil_defaultlib
+
+
+ SequenceStorage_stub.vhdl
+ vhdlSource
+ USED_IN_synth_blackbox_stub
+ xil_defaultlib
+
+
+ SequenceStorage_funcsim.v
+ verilogSource
+ USED_IN_simulation
+ USED_IN_single_language
+ xil_defaultlib
+
+
+ SequenceStorage_funcsim.vhdl
+ vhdlSource
+ USED_IN_simulation
+ USED_IN_single_language
+ xil_defaultlib
+
+
+
+ The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.
+
+
+ Component_Name
+ SequenceStorage
+
+
+
+ true
+
+
+
+
+
+ Interface_Type
+ Native
+
+
+
+ true
+
+
+
+
+
+ AXI_Type
+ AXI4_Full
+
+
+
+ true
+
+
+
+
+
+ AXI_Slave_Type
+ Memory_Slave
+
+
+
+ true
+
+
+
+
+
+ Use_AXI_ID
+ false
+
+
+
+ false
+
+
+
+
+
+ AXI_ID_Width
+ 4
+
+
+
+ false
+
+
+
+
+
+ Memory_Type
+ Single_Port_ROM
+
+
+
+ true
+
+
+
+
+
+ Enable_32bit_Address
+ false
+
+
+
+ true
+
+
+
+
+
+ ecctype
+ No_ECC
+
+
+
+ false
+
+
+
+
+
+ ECC
+ false
+
+
+
+ false
+
+
+
+
+
+ softecc
+ false
+
+
+
+ false
+
+
+
+
+
+ EN_SLEEP_PIN
+ false
+
+
+
+ true
+
+
+
+
+
+ EN_ECC_PIPE
+ false
+
+
+
+ false
+
+
+
+
+
+ Use_Error_Injection_Pins
+ false
+
+
+
+ false
+
+
+
+
+
+ Error_Injection_Type
+ Single_Bit_Error_Injection
+
+
+
+ false
+
+
+
+
+
+ Use_Byte_Write_Enable
+ false
+
+
+
+ false
+
+
+
+
+
+ Byte_Size
+ 9
+
+
+
+ false
+
+
+
+
+
+ Algorithm
+ Minimum_Area
+
+
+
+ true
+
+
+
+
+
+ Primitive
+ 8kx2
+
+
+
+ false
+
+
+
+
+
+ Assume_Synchronous_Clk
+ false
+
+
+
+ false
+
+
+
+
+
+ Write_Width_A
+ 16
+
+
+
+ true
+
+
+
+
+
+ Write_Depth_A
+ 9
+
+
+
+ true
+
+
+
+
+
+ Read_Width_A
+ 16
+
+
+
+ false
+
+
+
+
+
+ Operating_Mode_A
+ WRITE_FIRST
+
+
+
+ false
+
+
+
+
+
+ Enable_A
+ Always_Enabled
+
+
+
+ true
+
+
+
+
+
+ Write_Width_B
+ 16
+
+
+
+ false
+
+
+
+
+
+ Read_Width_B
+ 16
+
+
+
+ false
+
+
+
+
+
+ Operating_Mode_B
+ WRITE_FIRST
+
+
+
+ false
+
+
+
+
+
+ Enable_B
+ Always_Enabled
+
+
+
+ false
+
+
+
+
+
+ Register_PortA_Output_of_Memory_Primitives
+ true
+
+
+
+ true
+
+
+
+
+
+ Register_PortA_Output_of_Memory_Core
+ false
+
+
+
+ true
+
+
+
+
+
+ Use_REGCEA_Pin
+ false
+
+
+
+ true
+
+
+
+
+
+ Register_PortB_Output_of_Memory_Primitives
+ false
+
+
+
+ false
+
+
+
+
+
+ Register_PortB_Output_of_Memory_Core
+ false
+
+
+
+ false
+
+
+
+
+
+ Use_REGCEB_Pin
+ false
+
+
+
+ false
+
+
+
+
+
+ register_porta_input_of_softecc
+ false
+
+
+
+ false
+
+
+
+
+
+ register_portb_output_of_softecc
+ false
+
+
+
+ false
+
+
+
+
+
+ Pipeline_Stages
+ 0
+
+
+
+ false
+
+
+
+
+
+ Load_Init_File
+ true
+
+
+
+ true
+
+
+
+
+
+ Coe_File
+ ..\..\imports\Vivado\intialization.coe
+
+
+
+ true
+
+
+
+
+
+ Fill_Remaining_Memory_Locations
+ false
+
+
+
+ true
+
+
+
+
+
+ Remaining_Memory_Locations
+ 0
+
+
+
+ false
+
+
+
+
+
+ Use_RSTA_Pin
+ false
+
+
+
+ true
+
+
+
+
+
+ Reset_Memory_Latch_A
+ false
+
+
+
+ false
+
+
+
+
+
+ Reset_Priority_A
+ CE
+
+
+
+ false
+
+
+
+
+
+ Output_Reset_Value_A
+ 0
+
+
+
+ false
+
+
+
+
+
+ Use_RSTB_Pin
+ false
+
+
+
+ false
+
+
+
+
+
+ Reset_Memory_Latch_B
+ false
+
+
+
+ false
+
+
+
+
+
+ Reset_Priority_B
+ CE
+
+
+
+ false
+
+
+
+
+
+ Output_Reset_Value_B
+ 0
+
+
+
+ false
+
+
+
+
+
+ Reset_Type
+ SYNC
+
+
+
+ false
+
+
+
+
+
+ Additional_Inputs_for_Power_Estimation
+ false
+
+
+
+ true
+
+
+
+
+
+ Port_A_Clock
+ 100
+
+
+
+ true
+
+
+
+
+
+ Port_A_Write_Rate
+ 0
+
+
+
+ true
+
+
+
+
+
+ Port_B_Clock
+ 0
+
+
+
+ true
+
+
+
+
+
+ Port_B_Write_Rate
+ 0
+
+
+
+ true
+
+
+
+
+
+ Port_A_Enable_Rate
+ 100
+
+
+
+ true
+
+
+
+
+
+ Port_B_Enable_Rate
+ 0
+
+
+
+ true
+
+
+
+
+
+ Collision_Warnings
+ ALL
+
+
+
+ false
+
+
+
+
+
+ Disable_Collision_Warnings
+ false
+
+
+
+ true
+
+
+
+
+
+ Disable_Out_of_Range_Warnings
+ false
+
+
+
+ true
+
+
+
+
+
+ use_bram_block
+ Stand_Alone
+
+
+
+ true
+
+
+
+
+
+ MEM_FILE
+ no_mem_loaded
+
+
+
+ true
+
+
+
+
+
+ CTRL_ECC_ALGO
+ NONE
+
+
+
+ true
+
+
+
+
+
+
+
+
+ aartix7
+ artix7
+ artix7l
+ azynq
+ kintex7
+ kintex7l
+ kintexu
+ qartix7
+ qkintex7
+ qkintex7l
+ qvirtex7
+ qzynq
+ virtex7
+ virtexu
+ zynq
+
+
+ /Memories_&_Storage_Elements/RAMs_&_ROMs
+ /Basic_Elements/Memory_Elements
+
+ Block Memory Generator
+ 3
+ false
+
+ xilinx.com:ip:blk_mem_gen:7.1
+ xilinx.com:ip:blk_mem_gen:7.2
+ xilinx.com:ip:blk_mem_gen:7.3
+ xilinx.com:ip:blk_mem_gen:8.0
+ xilinx.com:ip:blk_mem_gen:8.1
+
+ 2014-11-18T07:59:48Z
+
+
+ 2014.4
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/ip/SequenceStorage/SequenceStorage_funcsim.v b/ip/SequenceStorage/SequenceStorage_funcsim.v
new file mode 100644
index 0000000..5971db1
--- /dev/null
+++ b/ip/SequenceStorage/SequenceStorage_funcsim.v
@@ -0,0 +1,738 @@
+// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2014.4 (win32) Build 1071353 Tue Nov 18 18:06:20 MST 2014
+// Date : Wed Jan 21 16:06:49 2015
+// Host : ul-win7-12 running 32-bit Service Pack 1 (build 7601)
+// Command : write_verilog -force -mode funcsim
+// C:/Users/ulab/Downloads/Lab_Project1.xpr/Lab_Project1/Lab_Project1.srcs/sources_1/ip/SequenceStorage/SequenceStorage_funcsim.v
+// Design : SequenceStorage
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7a100tcsg324-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "SequenceStorage,blk_mem_gen_v8_2,{}" *)
+(* core_generation_info = "SequenceStorage,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=SequenceStorage.mif,C_INIT_FILE=SequenceStorage.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=9,C_READ_DEPTH_A=9,C_ADDRA_WIDTH=4,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=9,C_READ_DEPTH_B=9,C_ADDRB_WIDTH=4,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.7096 mW}" *)
+(* NotValidForBitStream *)
+module SequenceStorage
+ (clka,
+ addra,
+ douta);
+ (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
+ input [3:0]addra;
+ output [15:0]douta;
+
+ wire [3:0]addra;
+ wire clka;
+ wire [15:0]douta;
+ wire NLW_U0_dbiterr_UNCONNECTED;
+ wire NLW_U0_s_axi_arready_UNCONNECTED;
+ wire NLW_U0_s_axi_awready_UNCONNECTED;
+ wire NLW_U0_s_axi_bvalid_UNCONNECTED;
+ wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
+ wire NLW_U0_s_axi_rlast_UNCONNECTED;
+ wire NLW_U0_s_axi_rvalid_UNCONNECTED;
+ wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
+ wire NLW_U0_s_axi_wready_UNCONNECTED;
+ wire NLW_U0_sbiterr_UNCONNECTED;
+ wire [15:0]NLW_U0_doutb_UNCONNECTED;
+ wire [3:0]NLW_U0_rdaddrecc_UNCONNECTED;
+ wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
+ wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
+ wire [3:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
+ wire [15:0]NLW_U0_s_axi_rdata_UNCONNECTED;
+ wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
+ wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
+
+(* C_ADDRA_WIDTH = "4" *)
+ (* C_ADDRB_WIDTH = "4" *)
+ (* C_ALGORITHM = "1" *)
+ (* C_AXI_ID_WIDTH = "4" *)
+ (* C_AXI_SLAVE_TYPE = "0" *)
+ (* C_AXI_TYPE = "1" *)
+ (* C_BYTE_SIZE = "9" *)
+ (* C_COMMON_CLK = "0" *)
+ (* C_COUNT_18K_BRAM = "1" *)
+ (* C_COUNT_36K_BRAM = "0" *)
+ (* C_CTRL_ECC_ALGO = "NONE" *)
+ (* C_DEFAULT_DATA = "0" *)
+ (* C_DISABLE_WARN_BHV_COLL = "0" *)
+ (* C_DISABLE_WARN_BHV_RANGE = "0" *)
+ (* C_ELABORATION_DIR = "./" *)
+ (* C_ENABLE_32BIT_ADDRESS = "0" *)
+ (* C_EN_ECC_PIPE = "0" *)
+ (* C_EN_SLEEP_PIN = "0" *)
+ (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.7096 mW" *)
+ (* C_FAMILY = "artix7" *)
+ (* C_HAS_AXI_ID = "0" *)
+ (* C_HAS_ENA = "0" *)
+ (* C_HAS_ENB = "0" *)
+ (* C_HAS_INJECTERR = "0" *)
+ (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
+ (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
+ (* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
+ (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
+ (* C_HAS_REGCEA = "0" *)
+ (* C_HAS_REGCEB = "0" *)
+ (* C_HAS_RSTA = "0" *)
+ (* C_HAS_RSTB = "0" *)
+ (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
+ (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
+ (* C_INITA_VAL = "0" *)
+ (* C_INITB_VAL = "0" *)
+ (* C_INIT_FILE = "SequenceStorage.mem" *)
+ (* C_INIT_FILE_NAME = "SequenceStorage.mif" *)
+ (* C_INTERFACE_TYPE = "0" *)
+ (* C_LOAD_INIT_FILE = "1" *)
+ (* C_MEM_TYPE = "3" *)
+ (* C_MUX_PIPELINE_STAGES = "0" *)
+ (* C_PRIM_TYPE = "1" *)
+ (* C_READ_DEPTH_A = "9" *)
+ (* C_READ_DEPTH_B = "9" *)
+ (* C_READ_WIDTH_A = "16" *)
+ (* C_READ_WIDTH_B = "16" *)
+ (* C_RSTRAM_A = "0" *)
+ (* C_RSTRAM_B = "0" *)
+ (* C_RST_PRIORITY_A = "CE" *)
+ (* C_RST_PRIORITY_B = "CE" *)
+ (* C_SIM_COLLISION_CHECK = "ALL" *)
+ (* C_USE_BRAM_BLOCK = "0" *)
+ (* C_USE_BYTE_WEA = "0" *)
+ (* C_USE_BYTE_WEB = "0" *)
+ (* C_USE_DEFAULT_DATA = "0" *)
+ (* C_USE_ECC = "0" *)
+ (* C_USE_SOFTECC = "0" *)
+ (* C_WEA_WIDTH = "1" *)
+ (* C_WEB_WIDTH = "1" *)
+ (* C_WRITE_DEPTH_A = "9" *)
+ (* C_WRITE_DEPTH_B = "9" *)
+ (* C_WRITE_MODE_A = "WRITE_FIRST" *)
+ (* C_WRITE_MODE_B = "WRITE_FIRST" *)
+ (* C_WRITE_WIDTH_A = "16" *)
+ (* C_WRITE_WIDTH_B = "16" *)
+ (* C_XDEVICEFAMILY = "artix7" *)
+ (* DONT_TOUCH *)
+ (* downgradeipidentifiedwarnings = "yes" *)
+ SequenceStorage_blk_mem_gen_v8_2__parameterized0 U0
+ (.addra(addra),
+ .addrb({1'b0,1'b0,1'b0,1'b0}),
+ .clka(clka),
+ .clkb(1'b0),
+ .dbiterr(NLW_U0_dbiterr_UNCONNECTED),
+ .dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .douta(douta),
+ .doutb(NLW_U0_doutb_UNCONNECTED[15:0]),
+ .eccpipece(1'b0),
+ .ena(1'b0),
+ .enb(1'b0),
+ .injectdbiterr(1'b0),
+ .injectsbiterr(1'b0),
+ .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[3:0]),
+ .regcea(1'b0),
+ .regceb(1'b0),
+ .rsta(1'b0),
+ .rstb(1'b0),
+ .s_aclk(1'b0),
+ .s_aresetn(1'b0),
+ .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_arburst({1'b0,1'b0}),
+ .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
+ .s_axi_arsize({1'b0,1'b0,1'b0}),
+ .s_axi_arvalid(1'b0),
+ .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_awburst({1'b0,1'b0}),
+ .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
+ .s_axi_awsize({1'b0,1'b0,1'b0}),
+ .s_axi_awvalid(1'b0),
+ .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
+ .s_axi_bready(1'b0),
+ .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
+ .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
+ .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
+ .s_axi_injectdbiterr(1'b0),
+ .s_axi_injectsbiterr(1'b0),
+ .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[3:0]),
+ .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[15:0]),
+ .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
+ .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
+ .s_axi_rready(1'b0),
+ .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
+ .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
+ .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
+ .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_wlast(1'b0),
+ .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
+ .s_axi_wstrb(1'b0),
+ .s_axi_wvalid(1'b0),
+ .sbiterr(NLW_U0_sbiterr_UNCONNECTED),
+ .sleep(1'b0),
+ .wea(1'b0),
+ .web(1'b0));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
+module SequenceStorage_blk_mem_gen_generic_cstr
+ (douta,
+ clka,
+ addra);
+ output [15:0]douta;
+ input clka;
+ input [3:0]addra;
+
+ wire [3:0]addra;
+ wire clka;
+ wire [15:0]douta;
+
+SequenceStorage_blk_mem_gen_prim_width \ramloop[0].ram.r
+ (.addra(addra),
+ .clka(clka),
+ .douta(douta));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
+module SequenceStorage_blk_mem_gen_prim_width
+ (douta,
+ clka,
+ addra);
+ output [15:0]douta;
+ input clka;
+ input [3:0]addra;
+
+ wire [3:0]addra;
+ wire clka;
+ wire [15:0]douta;
+
+SequenceStorage_blk_mem_gen_prim_wrapper_init \prim_init.ram
+ (.addra(addra),
+ .clka(clka),
+ .douta(douta));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
+module SequenceStorage_blk_mem_gen_prim_wrapper_init
+ (douta,
+ clka,
+ addra);
+ output [15:0]douta;
+ input clka;
+ input [3:0]addra;
+
+ wire [3:0]addra;
+ wire clka;
+ wire [15:0]douta;
+ wire \n_0_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_10_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_11_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_16_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_17_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_18_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_19_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_1_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_24_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_25_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_26_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_27_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_2_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_32_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_33_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_34_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_35_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_3_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_8_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+ wire \n_9_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
+
+(* box_type = "PRIMITIVE" *)
+ RAMB18E1 #(
+ .DOA_REG(1),
+ .DOB_REG(1),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0D0E0A0D0F0E0E0D0C0C0D0D0A0A0B0B0F0E040505000500000A000A00000000),
+ .INIT_01(256'h000000000000000000000000000000000000000000000000000000000B0E0E0F),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(18'h00000),
+ .INIT_B(18'h00000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
+ .READ_WIDTH_A(18),
+ .READ_WIDTH_B(18),
+ .RSTREG_PRIORITY_A("REGCE"),
+ .RSTREG_PRIORITY_B("REGCE"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(18'h00000),
+ .SRVAL_B(18'h00000),
+ .WRITE_MODE_A("WRITE_FIRST"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(18),
+ .WRITE_WIDTH_B(18))
+ \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
+ (.ADDRARDADDR({1'b0,1'b0,1'b0,1'b0,1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
+ .CLKARDCLK(clka),
+ .CLKBWRCLK(clka),
+ .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0}),
+ .DIPBDIP({1'b0,1'b0}),
+ .DOADO({\n_0_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_1_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_2_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_3_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,douta[7:4],\n_8_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_9_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_10_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_11_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,douta[3:0]}),
+ .DOBDO({\n_16_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_17_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_18_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_19_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,douta[15:12],\n_24_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_25_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_26_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_27_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,douta[11:8]}),
+ .DOPADOP({\n_32_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_33_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram }),
+ .DOPBDOP({\n_34_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_35_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram }),
+ .ENARDEN(1'b1),
+ .ENBWREN(1'b1),
+ .REGCEAREGCE(1'b1),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .WEA({1'b0,1'b0}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_top" *)
+module SequenceStorage_blk_mem_gen_top
+ (douta,
+ clka,
+ addra);
+ output [15:0]douta;
+ input clka;
+ input [3:0]addra;
+
+ wire [3:0]addra;
+ wire clka;
+ wire [15:0]douta;
+
+SequenceStorage_blk_mem_gen_generic_cstr \valid.cstr
+ (.addra(addra),
+ .clka(clka),
+ .douta(douta));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* C_FAMILY = "artix7" *) (* C_XDEVICEFAMILY = "artix7" *)
+(* C_ELABORATION_DIR = "./" *) (* C_INTERFACE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
+(* C_AXI_SLAVE_TYPE = "0" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_ENABLE_32BIT_ADDRESS = "0" *)
+(* C_CTRL_ECC_ALGO = "NONE" *) (* C_HAS_AXI_ID = "0" *) (* C_AXI_ID_WIDTH = "4" *)
+(* C_MEM_TYPE = "3" *) (* C_BYTE_SIZE = "9" *) (* C_ALGORITHM = "1" *)
+(* C_PRIM_TYPE = "1" *) (* C_LOAD_INIT_FILE = "1" *) (* C_INIT_FILE_NAME = "SequenceStorage.mif" *)
+(* C_INIT_FILE = "SequenceStorage.mem" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_DEFAULT_DATA = "0" *)
+(* C_HAS_RSTA = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RSTRAM_A = "0" *)
+(* C_INITA_VAL = "0" *) (* C_HAS_ENA = "0" *) (* C_HAS_REGCEA = "0" *)
+(* C_USE_BYTE_WEA = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
+(* C_WRITE_WIDTH_A = "16" *) (* C_READ_WIDTH_A = "16" *) (* C_WRITE_DEPTH_A = "9" *)
+(* C_READ_DEPTH_A = "9" *) (* C_ADDRA_WIDTH = "4" *) (* C_HAS_RSTB = "0" *)
+(* C_RST_PRIORITY_B = "CE" *) (* C_RSTRAM_B = "0" *) (* C_INITB_VAL = "0" *)
+(* C_HAS_ENB = "0" *) (* C_HAS_REGCEB = "0" *) (* C_USE_BYTE_WEB = "0" *)
+(* C_WEB_WIDTH = "1" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_B = "16" *)
+(* C_READ_WIDTH_B = "16" *) (* C_WRITE_DEPTH_B = "9" *) (* C_READ_DEPTH_B = "9" *)
+(* C_ADDRB_WIDTH = "4" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
+(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *)
+(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_USE_SOFTECC = "0" *)
+(* C_USE_ECC = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_HAS_INJECTERR = "0" *)
+(* C_SIM_COLLISION_CHECK = "ALL" *) (* C_COMMON_CLK = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *)
+(* C_EN_SLEEP_PIN = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_COUNT_36K_BRAM = "0" *)
+(* C_COUNT_18K_BRAM = "1" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.7096 mW" *) (* downgradeipidentifiedwarnings = "yes" *)
+module SequenceStorage_blk_mem_gen_v8_2__parameterized0
+ (clka,
+ rsta,
+ ena,
+ regcea,
+ wea,
+ addra,
+ dina,
+ douta,
+ clkb,
+ rstb,
+ enb,
+ regceb,
+ web,
+ addrb,
+ dinb,
+ doutb,
+ injectsbiterr,
+ injectdbiterr,
+ eccpipece,
+ sbiterr,
+ dbiterr,
+ rdaddrecc,
+ sleep,
+ s_aclk,
+ s_aresetn,
+ s_axi_awid,
+ s_axi_awaddr,
+ s_axi_awlen,
+ s_axi_awsize,
+ s_axi_awburst,
+ s_axi_awvalid,
+ s_axi_awready,
+ s_axi_wdata,
+ s_axi_wstrb,
+ s_axi_wlast,
+ s_axi_wvalid,
+ s_axi_wready,
+ s_axi_bid,
+ s_axi_bresp,
+ s_axi_bvalid,
+ s_axi_bready,
+ s_axi_arid,
+ s_axi_araddr,
+ s_axi_arlen,
+ s_axi_arsize,
+ s_axi_arburst,
+ s_axi_arvalid,
+ s_axi_arready,
+ s_axi_rid,
+ s_axi_rdata,
+ s_axi_rresp,
+ s_axi_rlast,
+ s_axi_rvalid,
+ s_axi_rready,
+ s_axi_injectsbiterr,
+ s_axi_injectdbiterr,
+ s_axi_sbiterr,
+ s_axi_dbiterr,
+ s_axi_rdaddrecc);
+ input clka;
+ input rsta;
+ input ena;
+ input regcea;
+ input [0:0]wea;
+ input [3:0]addra;
+ input [15:0]dina;
+ output [15:0]douta;
+ input clkb;
+ input rstb;
+ input enb;
+ input regceb;
+ input [0:0]web;
+ input [3:0]addrb;
+ input [15:0]dinb;
+ output [15:0]doutb;
+ input injectsbiterr;
+ input injectdbiterr;
+ input eccpipece;
+ output sbiterr;
+ output dbiterr;
+ output [3:0]rdaddrecc;
+ input sleep;
+ input s_aclk;
+ input s_aresetn;
+ input [3:0]s_axi_awid;
+ input [31:0]s_axi_awaddr;
+ input [7:0]s_axi_awlen;
+ input [2:0]s_axi_awsize;
+ input [1:0]s_axi_awburst;
+ input s_axi_awvalid;
+ output s_axi_awready;
+ input [15:0]s_axi_wdata;
+ input [0:0]s_axi_wstrb;
+ input s_axi_wlast;
+ input s_axi_wvalid;
+ output s_axi_wready;
+ output [3:0]s_axi_bid;
+ output [1:0]s_axi_bresp;
+ output s_axi_bvalid;
+ input s_axi_bready;
+ input [3:0]s_axi_arid;
+ input [31:0]s_axi_araddr;
+ input [7:0]s_axi_arlen;
+ input [2:0]s_axi_arsize;
+ input [1:0]s_axi_arburst;
+ input s_axi_arvalid;
+ output s_axi_arready;
+ output [3:0]s_axi_rid;
+ output [15:0]s_axi_rdata;
+ output [1:0]s_axi_rresp;
+ output s_axi_rlast;
+ output s_axi_rvalid;
+ input s_axi_rready;
+ input s_axi_injectsbiterr;
+ input s_axi_injectdbiterr;
+ output s_axi_sbiterr;
+ output s_axi_dbiterr;
+ output [3:0]s_axi_rdaddrecc;
+
+ wire \ ;
+ wire [3:0]addra;
+ wire [3:0]addrb;
+ wire clka;
+ wire clkb;
+ wire [15:0]dina;
+ wire [15:0]dinb;
+ wire [15:0]douta;
+ wire eccpipece;
+ wire ena;
+ wire enb;
+ wire injectdbiterr;
+ wire injectsbiterr;
+ wire regcea;
+ wire regceb;
+ wire rsta;
+ wire rstb;
+ wire s_aclk;
+ wire s_aresetn;
+ wire [31:0]s_axi_araddr;
+ wire [1:0]s_axi_arburst;
+ wire [3:0]s_axi_arid;
+ wire [7:0]s_axi_arlen;
+ wire [2:0]s_axi_arsize;
+ wire s_axi_arvalid;
+ wire [31:0]s_axi_awaddr;
+ wire [1:0]s_axi_awburst;
+ wire [3:0]s_axi_awid;
+ wire [7:0]s_axi_awlen;
+ wire [2:0]s_axi_awsize;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire s_axi_injectdbiterr;
+ wire s_axi_injectsbiterr;
+ wire s_axi_rready;
+ wire [15:0]s_axi_wdata;
+ wire s_axi_wlast;
+ wire [0:0]s_axi_wstrb;
+ wire s_axi_wvalid;
+ wire sleep;
+ wire [0:0]wea;
+ wire [0:0]web;
+
+ assign dbiterr = \ ;
+ assign doutb[15] = \ ;
+ assign doutb[14] = \ ;
+ assign doutb[13] = \ ;
+ assign doutb[12] = \ ;
+ assign doutb[11] = \ ;
+ assign doutb[10] = \ ;
+ assign doutb[9] = \ ;
+ assign doutb[8] = \ ;
+ assign doutb[7] = \ ;
+ assign doutb[6] = \ ;
+ assign doutb[5] = \ ;
+ assign doutb[4] = \ ;
+ assign doutb[3] = \ ;
+ assign doutb[2] = \ ;
+ assign doutb[1] = \ ;
+ assign doutb[0] = \ ;
+ assign rdaddrecc[3] = \ ;
+ assign rdaddrecc[2] = \ ;
+ assign rdaddrecc[1] = \ ;
+ assign rdaddrecc[0] = \ ;
+ assign s_axi_arready = \ ;
+ assign s_axi_awready = \ ;
+ assign s_axi_bid[3] = \ ;
+ assign s_axi_bid[2] = \ ;
+ assign s_axi_bid[1] = \ ;
+ assign s_axi_bid[0] = \ ;
+ assign s_axi_bresp[1] = \ ;
+ assign s_axi_bresp[0] = \ ;
+ assign s_axi_bvalid = \ ;
+ assign s_axi_dbiterr = \ ;
+ assign s_axi_rdaddrecc[3] = \ ;
+ assign s_axi_rdaddrecc[2] = \ ;
+ assign s_axi_rdaddrecc[1] = \ ;
+ assign s_axi_rdaddrecc[0] = \ ;
+ assign s_axi_rdata[15] = \ ;
+ assign s_axi_rdata[14] = \ ;
+ assign s_axi_rdata[13] = \ ;
+ assign s_axi_rdata[12] = \ ;
+ assign s_axi_rdata[11] = \ ;
+ assign s_axi_rdata[10] = \ ;
+ assign s_axi_rdata[9] = \ ;
+ assign s_axi_rdata[8] = \ ;
+ assign s_axi_rdata[7] = \ ;
+ assign s_axi_rdata[6] = \ ;
+ assign s_axi_rdata[5] = \ ;
+ assign s_axi_rdata[4] = \ ;
+ assign s_axi_rdata[3] = \ ;
+ assign s_axi_rdata[2] = \ ;
+ assign s_axi_rdata[1] = \ ;
+ assign s_axi_rdata[0] = \ ;
+ assign s_axi_rid[3] = \ ;
+ assign s_axi_rid[2] = \ ;
+ assign s_axi_rid[1] = \ ;
+ assign s_axi_rid[0] = \ ;
+ assign s_axi_rlast = \ ;
+ assign s_axi_rresp[1] = \ ;
+ assign s_axi_rresp[0] = \ ;
+ assign s_axi_rvalid = \ ;
+ assign s_axi_sbiterr = \ ;
+ assign s_axi_wready = \ ;
+ assign sbiterr = \ ;
+GND GND
+ (.G(\ ));
+SequenceStorage_blk_mem_gen_v8_2_synth inst_blk_mem_gen
+ (.addra(addra),
+ .clka(clka),
+ .douta(douta));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
+module SequenceStorage_blk_mem_gen_v8_2_synth
+ (douta,
+ clka,
+ addra);
+ output [15:0]douta;
+ input clka;
+ input [3:0]addra;
+
+ wire [3:0]addra;
+ wire clka;
+ wire [15:0]douta;
+
+SequenceStorage_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
+ (.addra(addra),
+ .clka(clka),
+ .douta(douta));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/ip/SequenceStorage/SequenceStorage_funcsim.vhdl b/ip/SequenceStorage/SequenceStorage_funcsim.vhdl
new file mode 100644
index 0000000..67034e6
--- /dev/null
+++ b/ip/SequenceStorage/SequenceStorage_funcsim.vhdl
@@ -0,0 +1,1005 @@
+-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2014.4 (win32) Build 1071353 Tue Nov 18 18:06:20 MST 2014
+-- Date : Wed Jan 21 16:06:49 2015
+-- Host : ul-win7-12 running 32-bit Service Pack 1 (build 7601)
+-- Command : write_vhdl -force -mode funcsim
+-- C:/Users/ulab/Downloads/Lab_Project1.xpr/Lab_Project1/Lab_Project1.srcs/sources_1/ip/SequenceStorage/SequenceStorage_funcsim.vhdl
+-- Design : SequenceStorage
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7a100tcsg324-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity SequenceStorage_blk_mem_gen_prim_wrapper_init is
+ port (
+ douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ clka : in STD_LOGIC;
+ addra : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of SequenceStorage_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
+end SequenceStorage_blk_mem_gen_prim_wrapper_init;
+
+architecture STRUCTURE of SequenceStorage_blk_mem_gen_prim_wrapper_init is
+ signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_10_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_11_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_17_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_18_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_19_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_1_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_25_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_26_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_27_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_2_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_3_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ signal \n_9_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
+ attribute box_type : string;
+ attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
+begin
+\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
+ generic map(
+ DOA_REG => 1,
+ DOB_REG => 1,
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_00 => X"0D0E0A0D0F0E0E0D0C0C0D0D0A0A0B0B0F0E040505000500000A000A00000000",
+ INIT_01 => X"000000000000000000000000000000000000000000000000000000000B0E0E0F",
+ INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_A => X"00000",
+ INIT_B => X"00000",
+ INIT_FILE => "NONE",
+ IS_CLKARDCLK_INVERTED => '0',
+ IS_CLKBWRCLK_INVERTED => '0',
+ IS_ENARDEN_INVERTED => '0',
+ IS_ENBWREN_INVERTED => '0',
+ IS_RSTRAMARSTRAM_INVERTED => '0',
+ IS_RSTRAMB_INVERTED => '0',
+ IS_RSTREGARSTREG_INVERTED => '0',
+ IS_RSTREGB_INVERTED => '0',
+ RAM_MODE => "TDP",
+ RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
+ READ_WIDTH_A => 18,
+ READ_WIDTH_B => 18,
+ RSTREG_PRIORITY_A => "REGCE",
+ RSTREG_PRIORITY_B => "REGCE",
+ SIM_COLLISION_CHECK => "ALL",
+ SIM_DEVICE => "7SERIES",
+ SRVAL_A => X"00000",
+ SRVAL_B => X"00000",
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ WRITE_WIDTH_A => 18,
+ WRITE_WIDTH_B => 18
+ )
+ port map (
+ ADDRARDADDR(13) => '0',
+ ADDRARDADDR(12) => '0',
+ ADDRARDADDR(11) => '0',
+ ADDRARDADDR(10) => '0',
+ ADDRARDADDR(9) => '0',
+ ADDRARDADDR(8 downto 5) => addra(3 downto 0),
+ ADDRARDADDR(4) => '0',
+ ADDRARDADDR(3) => '0',
+ ADDRARDADDR(2) => '0',
+ ADDRARDADDR(1) => '0',
+ ADDRARDADDR(0) => '0',
+ ADDRBWRADDR(13) => '0',
+ ADDRBWRADDR(12) => '0',
+ ADDRBWRADDR(11) => '0',
+ ADDRBWRADDR(10) => '0',
+ ADDRBWRADDR(9) => '0',
+ ADDRBWRADDR(8 downto 5) => addra(3 downto 0),
+ ADDRBWRADDR(4) => '1',
+ ADDRBWRADDR(3) => '0',
+ ADDRBWRADDR(2) => '0',
+ ADDRBWRADDR(1) => '0',
+ ADDRBWRADDR(0) => '0',
+ CLKARDCLK => clka,
+ CLKBWRCLK => clka,
+ DIADI(15) => '0',
+ DIADI(14) => '0',
+ DIADI(13) => '0',
+ DIADI(12) => '0',
+ DIADI(11) => '0',
+ DIADI(10) => '0',
+ DIADI(9) => '0',
+ DIADI(8) => '0',
+ DIADI(7) => '0',
+ DIADI(6) => '0',
+ DIADI(5) => '0',
+ DIADI(4) => '0',
+ DIADI(3) => '0',
+ DIADI(2) => '0',
+ DIADI(1) => '0',
+ DIADI(0) => '0',
+ DIBDI(15) => '0',
+ DIBDI(14) => '0',
+ DIBDI(13) => '0',
+ DIBDI(12) => '0',
+ DIBDI(11) => '0',
+ DIBDI(10) => '0',
+ DIBDI(9) => '0',
+ DIBDI(8) => '0',
+ DIBDI(7) => '0',
+ DIBDI(6) => '0',
+ DIBDI(5) => '0',
+ DIBDI(4) => '0',
+ DIBDI(3) => '0',
+ DIBDI(2) => '0',
+ DIBDI(1) => '0',
+ DIBDI(0) => '0',
+ DIPADIP(1) => '0',
+ DIPADIP(0) => '0',
+ DIPBDIP(1) => '0',
+ DIPBDIP(0) => '0',
+ DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOADO(14) => \n_1_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOADO(13) => \n_2_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOADO(12) => \n_3_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOADO(11 downto 8) => douta(7 downto 4),
+ DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOADO(6) => \n_9_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOADO(5) => \n_10_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOADO(4) => \n_11_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOADO(3 downto 0) => douta(3 downto 0),
+ DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOBDO(14) => \n_17_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOBDO(13) => \n_18_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOBDO(12) => \n_19_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOBDO(11 downto 8) => douta(15 downto 12),
+ DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOBDO(6) => \n_25_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOBDO(5) => \n_26_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOBDO(4) => \n_27_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOBDO(3 downto 0) => douta(11 downto 8),
+ DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
+ ENARDEN => '1',
+ ENBWREN => '1',
+ REGCEAREGCE => '1',
+ REGCEB => '1',
+ RSTRAMARSTRAM => '0',
+ RSTRAMB => '0',
+ RSTREGARSTREG => '0',
+ RSTREGB => '0',
+ WEA(1) => '0',
+ WEA(0) => '0',
+ WEBWE(3) => '0',
+ WEBWE(2) => '0',
+ WEBWE(1) => '0',
+ WEBWE(0) => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity SequenceStorage_blk_mem_gen_prim_width is
+ port (
+ douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ clka : in STD_LOGIC;
+ addra : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of SequenceStorage_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
+end SequenceStorage_blk_mem_gen_prim_width;
+
+architecture STRUCTURE of SequenceStorage_blk_mem_gen_prim_width is
+begin
+\prim_init.ram\: entity work.SequenceStorage_blk_mem_gen_prim_wrapper_init
+ port map (
+ addra(3 downto 0) => addra(3 downto 0),
+ clka => clka,
+ douta(15 downto 0) => douta(15 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity SequenceStorage_blk_mem_gen_generic_cstr is
+ port (
+ douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ clka : in STD_LOGIC;
+ addra : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of SequenceStorage_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
+end SequenceStorage_blk_mem_gen_generic_cstr;
+
+architecture STRUCTURE of SequenceStorage_blk_mem_gen_generic_cstr is
+begin
+\ramloop[0].ram.r\: entity work.SequenceStorage_blk_mem_gen_prim_width
+ port map (
+ addra(3 downto 0) => addra(3 downto 0),
+ clka => clka,
+ douta(15 downto 0) => douta(15 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity SequenceStorage_blk_mem_gen_top is
+ port (
+ douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ clka : in STD_LOGIC;
+ addra : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of SequenceStorage_blk_mem_gen_top : entity is "blk_mem_gen_top";
+end SequenceStorage_blk_mem_gen_top;
+
+architecture STRUCTURE of SequenceStorage_blk_mem_gen_top is
+begin
+\valid.cstr\: entity work.SequenceStorage_blk_mem_gen_generic_cstr
+ port map (
+ addra(3 downto 0) => addra(3 downto 0),
+ clka => clka,
+ douta(15 downto 0) => douta(15 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity SequenceStorage_blk_mem_gen_v8_2_synth is
+ port (
+ douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ clka : in STD_LOGIC;
+ addra : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of SequenceStorage_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
+end SequenceStorage_blk_mem_gen_v8_2_synth;
+
+architecture STRUCTURE of SequenceStorage_blk_mem_gen_v8_2_synth is
+begin
+\gnativebmg.native_blk_mem_gen\: entity work.SequenceStorage_blk_mem_gen_top
+ port map (
+ addra(3 downto 0) => addra(3 downto 0),
+ clka => clka,
+ douta(15 downto 0) => douta(15 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ is
+ port (
+ clka : in STD_LOGIC;
+ rsta : in STD_LOGIC;
+ ena : in STD_LOGIC;
+ regcea : in STD_LOGIC;
+ wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+ addra : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ clkb : in STD_LOGIC;
+ rstb : in STD_LOGIC;
+ enb : in STD_LOGIC;
+ regceb : in STD_LOGIC;
+ web : in STD_LOGIC_VECTOR ( 0 to 0 );
+ addrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ injectsbiterr : in STD_LOGIC;
+ injectdbiterr : in STD_LOGIC;
+ eccpipece : in STD_LOGIC;
+ sbiterr : out STD_LOGIC;
+ dbiterr : out STD_LOGIC;
+ rdaddrecc : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ sleep : in STD_LOGIC;
+ s_aclk : in STD_LOGIC;
+ s_aresetn : in STD_LOGIC;
+ s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_wlast : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rlast : out STD_LOGIC;
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_injectsbiterr : in STD_LOGIC;
+ s_axi_injectdbiterr : in STD_LOGIC;
+ s_axi_sbiterr : out STD_LOGIC;
+ s_axi_dbiterr : out STD_LOGIC;
+ s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
+ attribute C_FAMILY : string;
+ attribute C_FAMILY of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
+ attribute C_XDEVICEFAMILY : string;
+ attribute C_XDEVICEFAMILY of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
+ attribute C_ELABORATION_DIR : string;
+ attribute C_ELABORATION_DIR of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "./";
+ attribute C_INTERFACE_TYPE : integer;
+ attribute C_INTERFACE_TYPE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_AXI_TYPE : integer;
+ attribute C_AXI_TYPE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
+ attribute C_AXI_SLAVE_TYPE : integer;
+ attribute C_AXI_SLAVE_TYPE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_USE_BRAM_BLOCK : integer;
+ attribute C_USE_BRAM_BLOCK of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_ENABLE_32BIT_ADDRESS : integer;
+ attribute C_ENABLE_32BIT_ADDRESS of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_CTRL_ECC_ALGO : string;
+ attribute C_CTRL_ECC_ALGO of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
+ attribute C_HAS_AXI_ID : integer;
+ attribute C_HAS_AXI_ID of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_AXI_ID_WIDTH : integer;
+ attribute C_AXI_ID_WIDTH of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
+ attribute C_MEM_TYPE : integer;
+ attribute C_MEM_TYPE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 3;
+ attribute C_BYTE_SIZE : integer;
+ attribute C_BYTE_SIZE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
+ attribute C_ALGORITHM : integer;
+ attribute C_ALGORITHM of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
+ attribute C_PRIM_TYPE : integer;
+ attribute C_PRIM_TYPE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
+ attribute C_LOAD_INIT_FILE : integer;
+ attribute C_LOAD_INIT_FILE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
+ attribute C_INIT_FILE_NAME : string;
+ attribute C_INIT_FILE_NAME of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "SequenceStorage.mif";
+ attribute C_INIT_FILE : string;
+ attribute C_INIT_FILE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "SequenceStorage.mem";
+ attribute C_USE_DEFAULT_DATA : integer;
+ attribute C_USE_DEFAULT_DATA of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_DEFAULT_DATA : string;
+ attribute C_DEFAULT_DATA of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
+ attribute C_HAS_RSTA : integer;
+ attribute C_HAS_RSTA of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_RST_PRIORITY_A : string;
+ attribute C_RST_PRIORITY_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
+ attribute C_RSTRAM_A : integer;
+ attribute C_RSTRAM_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_INITA_VAL : string;
+ attribute C_INITA_VAL of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
+ attribute C_HAS_ENA : integer;
+ attribute C_HAS_ENA of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_HAS_REGCEA : integer;
+ attribute C_HAS_REGCEA of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_USE_BYTE_WEA : integer;
+ attribute C_USE_BYTE_WEA of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_WEA_WIDTH : integer;
+ attribute C_WEA_WIDTH of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
+ attribute C_WRITE_MODE_A : string;
+ attribute C_WRITE_MODE_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
+ attribute C_WRITE_WIDTH_A : integer;
+ attribute C_WRITE_WIDTH_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 16;
+ attribute C_READ_WIDTH_A : integer;
+ attribute C_READ_WIDTH_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 16;
+ attribute C_WRITE_DEPTH_A : integer;
+ attribute C_WRITE_DEPTH_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
+ attribute C_READ_DEPTH_A : integer;
+ attribute C_READ_DEPTH_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
+ attribute C_ADDRA_WIDTH : integer;
+ attribute C_ADDRA_WIDTH of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
+ attribute C_HAS_RSTB : integer;
+ attribute C_HAS_RSTB of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_RST_PRIORITY_B : string;
+ attribute C_RST_PRIORITY_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
+ attribute C_RSTRAM_B : integer;
+ attribute C_RSTRAM_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_INITB_VAL : string;
+ attribute C_INITB_VAL of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
+ attribute C_HAS_ENB : integer;
+ attribute C_HAS_ENB of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_HAS_REGCEB : integer;
+ attribute C_HAS_REGCEB of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_USE_BYTE_WEB : integer;
+ attribute C_USE_BYTE_WEB of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_WEB_WIDTH : integer;
+ attribute C_WEB_WIDTH of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
+ attribute C_WRITE_MODE_B : string;
+ attribute C_WRITE_MODE_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
+ attribute C_WRITE_WIDTH_B : integer;
+ attribute C_WRITE_WIDTH_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 16;
+ attribute C_READ_WIDTH_B : integer;
+ attribute C_READ_WIDTH_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 16;
+ attribute C_WRITE_DEPTH_B : integer;
+ attribute C_WRITE_DEPTH_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
+ attribute C_READ_DEPTH_B : integer;
+ attribute C_READ_DEPTH_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
+ attribute C_ADDRB_WIDTH : integer;
+ attribute C_ADDRB_WIDTH of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
+ attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
+ attribute C_HAS_MEM_OUTPUT_REGS_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
+ attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
+ attribute C_HAS_MEM_OUTPUT_REGS_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
+ attribute C_HAS_MUX_OUTPUT_REGS_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
+ attribute C_HAS_MUX_OUTPUT_REGS_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_MUX_PIPELINE_STAGES : integer;
+ attribute C_MUX_PIPELINE_STAGES of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
+ attribute C_HAS_SOFTECC_INPUT_REGS_A of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
+ attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_USE_SOFTECC : integer;
+ attribute C_USE_SOFTECC of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_USE_ECC : integer;
+ attribute C_USE_ECC of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_EN_ECC_PIPE : integer;
+ attribute C_EN_ECC_PIPE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_HAS_INJECTERR : integer;
+ attribute C_HAS_INJECTERR of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_SIM_COLLISION_CHECK : string;
+ attribute C_SIM_COLLISION_CHECK of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
+ attribute C_COMMON_CLK : integer;
+ attribute C_COMMON_CLK of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_DISABLE_WARN_BHV_COLL : integer;
+ attribute C_DISABLE_WARN_BHV_COLL of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_EN_SLEEP_PIN : integer;
+ attribute C_EN_SLEEP_PIN of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_DISABLE_WARN_BHV_RANGE : integer;
+ attribute C_DISABLE_WARN_BHV_RANGE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
+ attribute C_COUNT_36K_BRAM : string;
+ attribute C_COUNT_36K_BRAM of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
+ attribute C_COUNT_18K_BRAM : string;
+ attribute C_COUNT_18K_BRAM of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "1";
+ attribute C_EST_POWER_SUMMARY : string;
+ attribute C_EST_POWER_SUMMARY of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 2.7096 mW";
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
+end \SequenceStorage_blk_mem_gen_v8_2__parameterized0\;
+
+architecture STRUCTURE of \SequenceStorage_blk_mem_gen_v8_2__parameterized0\ is
+ signal \\ : STD_LOGIC;
+begin
+ dbiterr <= \\;
+ doutb(15) <= \\;
+ doutb(14) <= \\;
+ doutb(13) <= \\;
+ doutb(12) <= \\;
+ doutb(11) <= \\;
+ doutb(10) <= \\;
+ doutb(9) <= \\;
+ doutb(8) <= \\;
+ doutb(7) <= \\;
+ doutb(6) <= \\;
+ doutb(5) <= \\;
+ doutb(4) <= \\;
+ doutb(3) <= \\;
+ doutb(2) <= \\;
+ doutb(1) <= \\;
+ doutb(0) <= \\;
+ rdaddrecc(3) <= \\;
+ rdaddrecc(2) <= \\;
+ rdaddrecc(1) <= \\;
+ rdaddrecc(0) <= \\;
+ s_axi_arready <= \\;
+ s_axi_awready <= \\;
+ s_axi_bid(3) <= \\;
+ s_axi_bid(2) <= \\;
+ s_axi_bid(1) <= \\;
+ s_axi_bid(0) <= \\;
+ s_axi_bresp(1) <= \\;
+ s_axi_bresp(0) <= \\;
+ s_axi_bvalid <= \\;
+ s_axi_dbiterr <= \\;
+ s_axi_rdaddrecc(3) <= \\;
+ s_axi_rdaddrecc(2) <= \\;
+ s_axi_rdaddrecc(1) <= \\;
+ s_axi_rdaddrecc(0) <= \\;
+ s_axi_rdata(15) <= \\;
+ s_axi_rdata(14) <= \\;
+ s_axi_rdata(13) <= \\;
+ s_axi_rdata(12) <= \\;
+ s_axi_rdata(11) <= \\;
+ s_axi_rdata(10) <= \\;
+ s_axi_rdata(9) <= \\;
+ s_axi_rdata(8) <= \\;
+ s_axi_rdata(7) <= \\;
+ s_axi_rdata(6) <= \\;
+ s_axi_rdata(5) <= \\;
+ s_axi_rdata(4) <= \\;
+ s_axi_rdata(3) <= \\;
+ s_axi_rdata(2) <= \\;
+ s_axi_rdata(1) <= \\;
+ s_axi_rdata(0) <= \\;
+ s_axi_rid(3) <= \\;
+ s_axi_rid(2) <= \\;
+ s_axi_rid(1) <= \\;
+ s_axi_rid(0) <= \\;
+ s_axi_rlast <= \\;
+ s_axi_rresp(1) <= \\;
+ s_axi_rresp(0) <= \\;
+ s_axi_rvalid <= \\;
+ s_axi_sbiterr <= \\;
+ s_axi_wready <= \\;
+ sbiterr <= \\;
+GND: unisim.vcomponents.GND
+ port map (
+ G => \