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A small 32-bit implementation of the RISC-V architecture
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site Various update regarding UART support documentation, FPGA programming… Aug 28, 2018
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README.md

Build Status Join the chat at https://gitter.im/rbarzic/nanorv32 Stories in Ready Stories in Backlog

nanorv32

A small 32-bit implementation of the RISC-V architecture

Highlights :

- 2-stage pipeline (fetch, execute)
- 2 AHB-lite  master interfaces (Code &  Data)
- lot of code is generated from a high level description
- written in verilog (using iverilog or Xilinx xvsim as simulator)
- RV32I ISA simulator available 

Still under development in dedicated branches:

  • RVC support
  • interrupt support (with auto push/pop of registers, like for Cortex-M)
  • debugger support

FPGA version available (Digilent ARTY board - Xilinx Artix7)

See http://rbarzic.github.io/nanorv32 for more information

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