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more fixes

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rdaly525 committed Nov 8, 2018
1 parent 1d296e1 commit 25ca08c55594dacea565825be8eb16977dbf45ab
Showing with 76 additions and 1 deletion.
  1. +1 −1 README.md
  2. 0 doc/{StandaloneCoireIR.md → Standalone.md}
  3. +75 −0 doc/coreirprims.csv
@@ -12,7 +12,7 @@
## Documentation

### Documentation for Users
* This [document](doc/StandaloneCoreIR.md) describes the standalone coreir tool (similar to LLVM's 'opt')
* This [document](doc/Standalone.md) describes the standalone coreir tool (similar to LLVM's 'opt')
* This is the [specification](doc/JsonSpec.md) for the CoreIR serialization format (hardware object file)
* This is a [specification](doc/coreirprims.csv) of CoreIR Primitives and Primitive Extentions

File renamed without changes.
@@ -0,0 +1,75 @@
Namespace,Category,Name(s),GenParams,ConfigParams,In interface,Out interface,GenParam Invarients,Comments
coreir,Bitwise,not,width : int,,in : BitIn[width],out : Bit[width],,
,,"and,or,xor",width : int,,"in0,in1 : BitIn[width]",out : Bit[width],,
,,"andr,orr,xorr",width : int,,"in0,in1 : BitIn[width]",out : Bit,,Bitwise Reduce
,,"shl,lshr,ashr ",width : int,,"in0,in1 : BitIn[width]",out : Bit[width],,Dynamic shift
,,,,,,,,
,Arithmetic,neg,width : int,,in : BitIn[width],out : Bit[width],,
,,"add,sub,mul",width : int,,"in0,in1 : BitIn[width]",out : Bit[width],,
,,"udiv,urem",width : int,,"in0,in1 : BitIn[width]",out : Bit[width],,
,,"sdiv,srem,smod",width : int,,"in0,in1 : BitIn[width]",out : Bit[width],,
,,,,,,,,
,Comp,eq,width : int,,"in0,in1 : BitIn[width]",out : Bit,,
,,"slt, sgt,sle,sge",width : int,,"in0,in1 : BitIn[width]",out : Bit,,
,,"ult,ugt,ule,uge",width : int,,"in0,in1 : BitIn[width]",out : Bit,,
,,mux,width : int,,"in0,in1 :BitIn[Width], sel : BitIn",out : Bit[width],,
,,,,,,,,
,State,regrst,width: int,init : BitVector<width>,"in : BitIn[width], clk : coreir.clkIn, rst : coreir.rstIn",out : Bit[width],,
,,reg,width : int,,"in : BitIn[width], clk : coreir.clkIn",out : Bit[width],,
,,,,,,,,
,Nocompute,const,width : int,value : BitVector<width>,,out : Bit[width],,
,,term,width : int,,in : BitIn[width],,,Terminate signal
,,slice,"width : int, lo : int, hi : int",,in : BitIn[width],out : Bit[hi-lo],0<=lo<=hi<width,Slice from a bit array
,,concat,"width0 : int, width1 : int",,"in0 : BitIn[width0], in1 : Bitin[width1]",out : Bit[width0+width1],,Concat two bit arrays together
,,wire,width : int,,in : BitIn[width],out : Bit[width],,
,,(NYI) repeat,"type : type, n : int",,in : type,out: type[n],,Repeat a type n times
,,(NYI) strip,ntype : type,,in : ntype,out : ntype.rawtype,ntype.isa(Named),Strip the named type
,,(NYI) wrap,ntype : type,,in : ntype.rawtype,out : ntype,ntype.isa(Named),wrap into named type
,,,,,,,,
corebit,,"and, or, xor",,,"in0,in1 : BitIn",out : Bit,,
,,"wire, not",,,in : BitIn,out : Bit,,
,,mux,,,"in0,in1 : BitIn, sel : BitIn",out : Bit,,
,,const,,value : Bool,,out : Bit,,
,,term,,,in : BitIn,,,
,,(NYI) dff ,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,,
,Comparison to QF_BV,,,,,,,
,Op,Direct support?,Indirect?,,,,,
,concat,1,,,,,,
,extract (slice),1,,,,,,
,not,1,,,,,,
,and,1,,,,,,
,or,1,,,,,,
,neg,1,,,,,,
,add,1,,,,,,
,mul,1,,,,,,
,udiv,1,,,,,,
,urem,1,,,,,,
,shl,1,,,,,,
,lshr,1,,,,,,
,ult,1,,,,,,
,nand,0,and->not,,,,,
,nor,0,or->not,,,,,
,xor,1,,,,,,
,xnor,0,xor->not,,,,,
,comp (eq),1,,,,,,
,sub,1,,,,,,
,sdiv,1,,,,,,
,srem,1,,,,,,
,smod,1,,,,,,
,ashr,1,,,,,,
,repeat,1,,,,,,
,zero_extend,0,"concat(const0,in)",,,,,
,sign_extend,0,"concat(repeat(in[msb]),in)",,,,,
,rotate_left,0,"concat(shl(1),in[msb])",,,,,
,rotate_right,0,"concat(in[0],lshr(1))",,,,,
,ule,1,,,,,,
,ugt,1,,,,,,
,slt,1,,,,,,
,sle,1,,,,,,
,sgt,1,,,,,,
,sge,1,,,,,,

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