Add pre-verilog pass to uniquify instance names to prevent aliasing with module port names.
Mar 31, 2020 by
Change all static string ID for passes to non-static
Feb 12, 2020 by
'primitive_type' attribute in verilog code is unsafe/bad style
Jan 13, 2020 by
'longname' when generator uses a CoreIR type as argument for generating verilog
Oct 16, 2019 by
CoreIR clock gated registers don't get inferred by synthesis tools
Oct 5, 2019 by
newDirectedModule does not return a new version after a pass has been run
Oct 2, 2019 by
ProTip! Type g p on any issue or pull request to go back to the pull request listing page.