From 927ee20a4ee54a20a61b2a058ae8a47b2597cba7 Mon Sep 17 00:00:00 2001 From: Ross Date: Wed, 8 Aug 2018 18:09:09 -0700 Subject: [PATCH 1/5] fixed syntax --- include/coreir/passes/transform/netify.h | 31 +++++++++++ src/passes/transform/netify.cpp | 67 ++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 include/coreir/passes/transform/netify.h create mode 100644 src/passes/transform/netify.cpp diff --git a/include/coreir/passes/transform/netify.h b/include/coreir/passes/transform/netify.h new file mode 100644 index 000000000..0ded8b24d --- /dev/null +++ b/include/coreir/passes/transform/netify.h @@ -0,0 +1,31 @@ +#ifndef COREIR_NETIFY_HPP_ +#define COREIR_NETIFY_HPP_ + +#include "coreir.h" + +//Define the analysis passes in CoreIR::Passes +namespace CoreIR { + + bool foldConstants(CoreIR::Module* const mod); + +namespace Passes { + + +//This will add directed connection metadata to modules +class Netify : public ModulePass { + + public: + static std::string ID; + Netify() : ModulePass(ID, "Transform circuit into netlist") {} + void setAnalysisInfo() override { + addDependency("verifyflattenedtypes"); + //addDependency("verifynobulkconnections"); + } + bool runOnModule(Module* m) override; +}; + +} +} + +#endif + diff --git a/src/passes/transform/netify.cpp b/src/passes/transform/netify.cpp new file mode 100644 index 000000000..1773f236b --- /dev/null +++ b/src/passes/transform/netify.cpp @@ -0,0 +1,67 @@ +#include "coreir.h" +#include "coreir/passes/transform/netify.h" + +using namespace std; +using namespace CoreIR; + +string Passes::Netify::ID = "netify"; + +namespace CoreIR { +namespace Passes { + + //Take all connections and a coreir-wire into it + bool Passes::Netify::runOnModule(Module* m) { + Context* c = getContext(); + ModuleDef* def = m->getDef(); + vector toRemove; + for (auto conn : def->getConnections()) { + Wireable* wa = conn.first; + Wireable* wb = conn.second; + + //First check if either end is an io port or a coreir wire + //if so, then do not need to add a wire + Wireable* waTop = wa->getTopParent(); + Wireable* wbTop = wb->getTopParent(); + if (isa(waTop) || isa(wbTop)) { + continue; + } + string aModKind = cast(waTop)->getModuleRef()->getRefName(); + string bModKind = cast(wbTop)->getModuleRef()->getRefName(); + if (aModKind == "coreir.wire" || aModKind == "corebit.wire") { + continue; + } + if (bModKind == "coreir.wire" || bModKind == "corebit.wire") { + continue; + } + + //Both ends of the connection are instances + Type* wtype = wa->getType(); + ASSERT(!wtype->isInOut() && !wtype->isMixed(),"NYI"); + Instance* wire; + if (auto at = dyn_cast(wtype)) { + int len = at->getLen(); + wire = def->addInstance("wire" + c->getUnique(),"coreir.wire",{{"width",Const::make(c,len)}}); + } + else { + ASSERT(wtype->isBaseType(),"Cannot handle non-base types"); + wire = def->addInstance("wire" + c->getUnique(),"corebit.wire"); + } + + if (wa->getType()->isInput()) { + def->connect(wa,wire->sel("out")); + def->connect(wb,wire->sel("in")); + } + else { + def->connect(wa,wire->sel("in")); + def->connect(wb,wire->sel("out")); + } + toRemove.push_back(conn); + } + for (auto conn : toRemove) { + def->disconnect(conn); + } + return toRemove.size()>0; + } + +} +} From fcec17d5f1f0c386855f762282667148f762fdf5 Mon Sep 17 00:00:00 2001 From: Ross Date: Wed, 8 Aug 2018 21:16:57 -0700 Subject: [PATCH 2/5] added netify to passes --- include/coreir/passes/analysis/vmodule.h | 4 ++-- include/coreir/passes/common.h | 2 ++ src/ir/module.cpp | 2 +- src/passes/analysis/verilog.cpp | 2 +- src/passes/transform/netify.cpp | 2 +- 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/coreir/passes/analysis/vmodule.h b/include/coreir/passes/analysis/vmodule.h index b6d722d5d..3043352b0 100644 --- a/include/coreir/passes/analysis/vmodule.h +++ b/include/coreir/passes/analysis/vmodule.h @@ -35,11 +35,11 @@ class VWire { VWire(Wireable* w) : VWire("",w->getType()) { SelectPath sp = w->getSelectPath(); if (sp.size()==3) { - ASSERT(dim==1 && !isNumber(sp[1]) && isNumber(sp[2]),"DEBUG ME:"); + ASSERT(dim==1 && !isNumber(sp[1]) && isNumber(sp[2]),"Bad vwire " + toString(sp)); name = sp[1]+"["+sp[2]+"]"; } else if (sp.size()==2) { - ASSERT(!isNumber(sp[1]),"DEBUG ME:"); + ASSERT(!isNumber(sp[1]),"Bad vwire " + toString(sp)); name = sp[1]; } else { diff --git a/include/coreir/passes/common.h b/include/coreir/passes/common.h index c8dffb024..6609437a3 100644 --- a/include/coreir/passes/common.h +++ b/include/coreir/passes/common.h @@ -44,6 +44,7 @@ #include "transform/adddirected.h" #include "transform/transform2combview.h" +#include "transform/netify.h" //TODO Macrofy this @@ -94,6 +95,7 @@ namespace CoreIR { pm.addPass(new Passes::RegisterInputs("registerinputs")); pm.addPass(new Passes::DeleteUnusedInouts("delete-unused-inouts")); pm.addPass(new Passes::Transform2CombView()); + pm.addPass(new Passes::Netify()); } } diff --git a/src/ir/module.cpp b/src/ir/module.cpp index c23a11d37..15c953c9d 100644 --- a/src/ir/module.cpp +++ b/src/ir/module.cpp @@ -76,7 +76,7 @@ void Module::setDef(ModuleDef* def, bool validate) { } string Module::toString() const { - return "Module: " + name + (isGenerated() ? ::CoreIR::toString(genargs) : "") + "\n Type: " + type->toString() + "\n Def? " + (hasDef() ? "Yes" : "No"); + return "Module: " + this->getRefName() + (isGenerated() ? ::CoreIR::toString(genargs) : "") + "\n Type: " + type->toString() + "\n Def? " + (hasDef() ? "Yes" : "No"); } bool Module::runGenerator() { diff --git a/src/passes/analysis/verilog.cpp b/src/passes/analysis/verilog.cpp index 726ac6bfa..806647e4a 100644 --- a/src/passes/analysis/verilog.cpp +++ b/src/passes/analysis/verilog.cpp @@ -68,7 +68,7 @@ bool Passes::Verilog::runOnInstanceGraphNode(InstanceGraphNode& node) { string iname = imap.first; Instance* inst = imap.second; Module* mref = imap.second->getModuleRef(); - ASSERT(modMap.count(mref),"DEBUG ME"); + ASSERT(modMap.count(mref),"Missing mod from inst" + toString(inst)); VModule* vref = modMap[mref]; vmod->addStmt(" //Wire declarations for instance '" + iname + "' (Module "+ vref->getName() + ")"); for (auto rmap : cast(imap.second->getType())->getRecord()) { diff --git a/src/passes/transform/netify.cpp b/src/passes/transform/netify.cpp index 1773f236b..a6c1582eb 100644 --- a/src/passes/transform/netify.cpp +++ b/src/passes/transform/netify.cpp @@ -60,7 +60,7 @@ namespace Passes { for (auto conn : toRemove) { def->disconnect(conn); } - return toRemove.size()>0; + return toRemove.size()>0 } } From 41e01180726733a1d20db6be0f7786257fed2f2b Mon Sep 17 00:00:00 2001 From: Ross Date: Thu, 9 Aug 2018 00:53:20 -0700 Subject: [PATCH 3/5] remobed prints --- include/coreir/definitions/coreVerilog.hpp | 2 -- src/ir/passmanager.cpp | 1 - src/passes/transform/netify.cpp | 2 +- 3 files changed, 1 insertion(+), 4 deletions(-) diff --git a/include/coreir/definitions/coreVerilog.hpp b/include/coreir/definitions/coreVerilog.hpp index 1e3b00cfb..fe8955bb1 100644 --- a/include/coreir/definitions/coreVerilog.hpp +++ b/include/coreir/definitions/coreVerilog.hpp @@ -186,8 +186,6 @@ void CoreIRLoadVerilog_coreir(Context* c) { "end\n" "assign out = outReg;"; core->getGenerator("reg_arst")->getMetaData()["verilog"] = vjson; - cout << "VJSON for reg: " << vjson << endl; - cout << "metadata for reg: " << core->getGenerator("reg_arst")->getMetaData() << endl; } { //reg diff --git a/src/ir/passmanager.cpp b/src/ir/passmanager.cpp index b9c6f1216..e4bfe2a87 100644 --- a/src/ir/passmanager.cpp +++ b/src/ir/passmanager.cpp @@ -125,7 +125,6 @@ bool PassManager::runPass(Pass* p,vector& pArgs) { for (int i=0; iaddInstance("wire" + c->getUnique(),"coreir.wire",{{"width",Const::make(c,len)}}); } else {