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omap: dispc: force L3_1 CD to NOSLEEP when dispc module is active.

With the DSS FIFO optimizations, ramdom lockups and reboots are seen. It has
been identified that L3_1 CD is idling and not responding to the traffic
initiated by DSS.  The Workaround suggested by Hardware team is to keep the
L3_1 CD in NO_SLEEP mode, when DSS is active.  Once DSS module is switched to
idle mode, put L3_1 CD to HW_AUTO.

This patch was reverted by 169c5f0, but
a test case was found that reproduces the original problem.

Change-Id: I7acfcaa407bc7a2423fcc7a82f3503a6fbcee331
Signed-off-by: Akash Choudhari <akashc@ti.com>
Signed-off-by: Avinash.H.M. <avinashhm@ti.com>
Signed-off-by: Sunita Nadampalli <sunitan@ti.com>
CC: Todd Poynor <toddpoynor@google.com>
CC: Colin Cross <ccross@android.com>
CC: Nishanth Menon <nm@ti.com>
CC: Girish S G <girishsg@ti.com>
CC: Mahesh <mahesh@ti.com>
CC: Dandawate Saket <dsaket@ti.com>
CC: Lajos Molnar <molnar@ti.com>
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1 parent 397236b commit 5664b3ba8c5187d605199f539fe036af470a9dde Avinash.H.M committed with colincross Oct 11, 2011
Showing with 21 additions and 0 deletions.
  1. +21 −0 drivers/video/omap2/dss/dispc.c
@@ -43,6 +43,7 @@
#include <plat/omap-pm.h>
#include <video/omapdss.h>
+#include "../clockdomain.h"
#include "dss.h"
#include "dss_features.h"
#include "dispc.h"
@@ -59,6 +60,8 @@
#define DISPC_MAX_NR_ISRS 8
+static struct clockdomain *l3_1_clkdm;
+
struct omap_dispc_isr_data {
omap_dispc_isr_t isr;
void *arg;
@@ -525,6 +528,15 @@ int dispc_runtime_get(void)
if (dispc.runtime_count++ == 0) {
DSSDBG("dispc_runtime_get\n");
+ /*
+ * With the DSS FIFO optimizations, ramdom lockups and reboots
+ * are seen. It has been identified that L3_1 CD is idling and
+ * not responding to the traffic initiated by DSS. The
+ * Workaround suggested by Hardware team is to keep the L3_1
+ * CD in NO_SLEEP mode, when DSS is active.
+ */
+ clkdm_deny_idle(l3_1_clkdm);
+
r = dss_runtime_get();
if (r)
goto err_dss_get;
@@ -570,6 +582,13 @@ void dispc_runtime_put(void)
clk_disable(dispc.dss_clk);
dss_runtime_put();
+
+ /*
+ * Restore the L3_1 CD to HW_AUTO, when DSS module idles.
+ * When DSS is idle, we can allow L3_1 to idle.
+ */
+ clkdm_allow_idle(l3_1_clkdm);
+
}
mutex_unlock(&dispc.runtime_lock);
@@ -3964,6 +3983,8 @@ static void _omap_dispc_initial_config(void)
dispc_write_reg(DISPC_DIVISOR, l);
}
+ l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
+
/* FUNCGATED */
if (dss_has_feature(FEAT_FUNCGATED))
REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);

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