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Schedule the interrupt signaling the end of an Aica DMA transfer #1412
referenced this pull request
Sep 27, 2018
This is definitely a step in the right direction. There's various nuances that we should implement, or at least assert about, like dma pauses, g1/g2 locks, and dma aborts.
This is much cleaner than other diffs I've seen trying to make DMAs take time.
@MrPsyMan do you think this should be included in the 18.10 release? I'd be wary to push it out without a thorough pass of 60/70 games myself, because of how easily timing can break games, and how much unimplemented functionality is exposed by making the DMA not be instant. I'm also wary that without asserts for unhandled cases we'll get 'silent breaks' that are only found out months later. Am I too cautious?
Isn't the purpose of this to do away with needing to configure it at all and actually fix the functionality, though? It seems like that would be 2 steps forward, one step back.