For installation instructions, see the README.
- integration layer for Verilator
- base infrastructure for verilated peripherals
- base class for verilated UARTs, with analyzer support
- Linux on LiteX with VexRiscv demo
- RISC-V CPUs now don't need CLINT in their constructor, but will accept any abstract time provider
- updated LiteX with PicoRV32 and LiteX with VexRibscv platform`
- sharing violation when trying to run downloaded files