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@PiotrZierhoffer PiotrZierhoffer released this May 15, 2019 · 97 commits to master since this release

For installation instructions, see the README.

Added:

  • integration layer for Verilator
  • base infrastructure for verilated peripherals
  • base class for verilated UARTs, with analyzer support
  • Linux on LiteX with VexRiscv demo

Changed:

  • RISC-V CPUs now don't need CLINT in their constructor, but will accept any abstract time provider
  • updated LiteX with PicoRV32 and LiteX with VexRibscv platform`

Fixed:

  • sharing violation when trying to run downloaded files
Assets 8
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