From af434f9316acc225b503a1d8a86d953f473901ed Mon Sep 17 00:00:00 2001
From: Alain Carlucci <alain@rev.ng>
Date: Thu, 26 Nov 2020 15:47:15 +0100
Subject: [PATCH 1/5] InstPrinter: Add AArch64 register markup

---
 .../MCTargetDesc/AArch64InstPrinter.cpp       | 143 +++++++++++-------
 .../AArch64/MCTargetDesc/AArch64InstPrinter.h |   1 +
 2 files changed, 93 insertions(+), 51 deletions(-)

diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 469892213ef8..7b34fdee2af2 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -53,7 +53,12 @@ AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
 
 void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
   // This is for .cfi directives.
-  OS << getRegisterName(RegNo);
+  OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
+}
+
+void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo, unsigned
+        AltIdx) const {
+  OS << markup("<reg:") << getRegisterName(RegNo, AltIdx) << markup(">");
 }
 
 void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
@@ -105,8 +110,10 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
       }
 
       if (AsmMnemonic) {
-        O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
-          << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
+        O << '\t' << AsmMnemonic << '\t';
+        printRegName(O, Op0.getReg());
+        O << ", ";
+        printRegName(O, getWRegFromXReg(Op1.getReg()));
         printAnnotation(O, Annot);
         return;
       }
@@ -141,8 +148,11 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
         shift = immr;
       }
       if (AsmMnemonic) {
-        O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
-          << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
+        O << '\t' << AsmMnemonic << '\t';
+        printRegName(O, Op0.getReg());
+        O << ", ";
+        printRegName(O, Op1.getReg());
+        O << ", #" << shift;
         printAnnotation(O, Annot);
         return;
       }
@@ -150,17 +160,22 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
 
     // SBFIZ/UBFIZ aliases
     if (Op2.getImm() > Op3.getImm()) {
-      O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
-        << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
-        << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
+      O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t';
+      printRegName(O, Op0.getReg());
+      O << ", ";
+      printRegName(O, Op1.getReg());
+      O << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #"
+        << Op3.getImm() + 1;
       printAnnotation(O, Annot);
       return;
     }
 
     // Otherwise SBFX/UBFX is the preferred form
-    O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
-      << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
-      << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
+    O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t';
+    printRegName(O, Op0.getReg());
+    O << ", ";
+    printRegName(O, Op1.getReg());
+    O << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
     printAnnotation(O, Annot);
     return;
   }
@@ -179,8 +194,9 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
       int LSB = (BitWidth - ImmR) % BitWidth;
       int Width = ImmS + 1;
 
-      O << "\tbfc\t" << getRegisterName(Op0.getReg())
-        << ", #" << LSB << ", #" << Width;
+      O << "\tbfc\t";
+      printRegName(O, Op0.getReg());
+      O << ", #" << LSB << ", #" << Width;
       printAnnotation(O, Annot);
       return;
     } else if (ImmS < ImmR) {
@@ -189,8 +205,11 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
       int LSB = (BitWidth - ImmR) % BitWidth;
       int Width = ImmS + 1;
 
-      O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
-        << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
+      O << "\tbfi\t";
+      printRegName(O, Op0.getReg());
+      O << ", ";
+      printRegName(O, Op2.getReg());
+      O << ", #" << LSB << ", #" << Width;
       printAnnotation(O, Annot);
       return;
     }
@@ -198,9 +217,11 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
     int LSB = ImmR;
     int Width = ImmS - ImmR + 1;
     // Otherwise BFXIL the preferred form
-    O << "\tbfxil\t"
-      << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
-      << ", #" << LSB << ", #" << Width;
+    O << "\tbfxil\t";
+    printRegName(O, Op0.getReg());
+    O << ", ";
+    printRegName(O, Op2.getReg());
+    O << ", #" << LSB << ", #" << Width;
     printAnnotation(O, Annot);
     return;
   }
@@ -216,14 +237,17 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
     else
       O << "\tmovn\t";
 
-    O << getRegisterName(MI->getOperand(0).getReg()) << ", #";
+    printRegName(O, MI->getOperand(0).getReg());
+    O << ", #";
     MI->getOperand(1).getExpr()->print(O, &MAI);
     return;
   }
 
   if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
       MI->getOperand(2).isExpr()) {
-    O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #";
+    O << "\tmovk\t";
+    printRegName(O, MI->getOperand(0).getReg());
+    O << ", #";
     MI->getOperand(2).getExpr()->print(O, &MAI);
     return;
   }
@@ -241,8 +265,9 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
 
     if (AArch64_AM::isMOVZMovAlias(Value, Shift,
                                    Opcode == AArch64::MOVZXi ? 64 : 32)) {
-      O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
-        << formatImm(SignExtend64(Value, RegWidth));
+      O << "\tmov\t";
+      printRegName(O, MI->getOperand(0).getReg());
+      O << ", #" << formatImm(SignExtend64(Value, RegWidth));
       return;
     }
   }
@@ -256,8 +281,9 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
       Value = Value & 0xffffffff;
 
     if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
-      O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
-        << formatImm(SignExtend64(Value, RegWidth));
+      O << "\tmov\t";
+      printRegName(O, MI->getOperand(0).getReg());
+      O << ", #" << formatImm(SignExtend64(Value, RegWidth));
       return;
     }
   }
@@ -270,8 +296,9 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
     uint64_t Value = AArch64_AM::decodeLogicalImmediate(
         MI->getOperand(2).getImm(), RegWidth);
     if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
-      O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
-        << formatImm(SignExtend64(Value, RegWidth));
+      O << "\tmov\t";
+      printRegName(O, MI->getOperand(0).getReg());
+      O << ", #" << formatImm(SignExtend64(Value, RegWidth));
       return;
     }
   }
@@ -713,14 +740,15 @@ void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
 
   bool IsTbx;
   if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
-    O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
-      << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
+    O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
+    printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
+    O << ", ";
 
     unsigned ListOpNum = IsTbx ? 2 : 1;
     printVectorList(MI, ListOpNum, STI, O, "");
 
-    O << ", "
-      << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
+    O << ", ";
+    printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
     printAnnotation(O, Annot);
     return;
   }
@@ -738,14 +766,17 @@ void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
 
     // Next the address: [xN]
     unsigned AddrReg = MI->getOperand(OpNum++).getReg();
-    O << ", [" << getRegisterName(AddrReg) << ']';
+    O << ", [";
+    printRegName(O, AddrReg);
+    O << ']';
 
     // Finally, there might be a post-indexed offset.
     if (LdStDesc->NaturalOffset != 0) {
       unsigned Reg = MI->getOperand(OpNum++).getReg();
-      if (Reg != AArch64::XZR)
-        O << ", " << getRegisterName(Reg);
-      else {
+      if (Reg != AArch64::XZR) {
+        O << ", ";
+        printRegName(O, Reg);
+      } else {
         assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
         O << ", #" << LdStDesc->NaturalOffset;
       }
@@ -865,8 +896,10 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
   std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
 
   O << '\t' << Str;
-  if (NeedsReg)
-    O << ", " << getRegisterName(MI->getOperand(4).getReg());
+  if (NeedsReg) {
+    O << ", ";
+    printRegName(O, MI->getOperand(4).getReg());
+  }
 
   return true;
 }
@@ -877,7 +910,7 @@ void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     unsigned Reg = Op.getReg();
-    O << getRegisterName(Reg);
+    printRegName(O, Reg);
   } else if (Op.isImm()) {
     printImm(MI, OpNo, STI, O);
   } else {
@@ -908,7 +941,7 @@ void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
     if (Reg == AArch64::XZR)
       O << "#" << Imm;
     else
-      O << getRegisterName(Reg);
+      printRegName(O, Reg);
   } else
     llvm_unreachable("unknown operand kind in printPostIncOperand64");
 }
@@ -919,7 +952,7 @@ void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
   const MCOperand &Op = MI->getOperand(OpNo);
   assert(Op.isReg() && "Non-register vreg operand!");
   unsigned Reg = Op.getReg();
-  O << getRegisterName(Reg, AArch64::vreg);
+  printRegName(O, Reg, AArch64::vreg);
 }
 
 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
@@ -976,14 +1009,14 @@ void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
 void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
                                               const MCSubtargetInfo &STI,
                                               raw_ostream &O) {
-  O << getRegisterName(MI->getOperand(OpNum).getReg());
+  printRegName(O, MI->getOperand(OpNum).getReg());
   printShifter(MI, OpNum + 1, STI, O);
 }
 
 void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
                                                const MCSubtargetInfo &STI,
                                                raw_ostream &O) {
-  O << getRegisterName(MI->getOperand(OpNum).getReg());
+  printRegName(O, MI->getOperand(OpNum).getReg());
   printArithExtend(MI, OpNum + 1, STI, O);
 }
 
@@ -1071,7 +1104,9 @@ void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
-  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
+  O << '[';
+  printRegName(O, MI->getOperand(OpNum).getReg());
+  O << ']';
 }
 
 template<int Scale>
@@ -1095,7 +1130,8 @@ void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
                                           unsigned Scale, raw_ostream &O) {
   const MCOperand MO1 = MI->getOperand(OpNum + 1);
-  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
+  O << '[';
+  printRegName(O, MI->getOperand(OpNum).getReg());
   if (MO1.isImm()) {
       O << ", #" << formatImm(MO1.getImm() * Scale);
   } else {
@@ -1251,7 +1287,9 @@ void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
 
   unsigned Even = MRI.getSubReg(Reg,  Sube);
   unsigned Odd = MRI.getSubReg(Reg,  Subo);
-  O << getRegisterName(Even) << ", " << getRegisterName(Odd);
+  printRegName(O, Even);
+  O << ", ";
+  printRegName(O, Odd);
 }
 
 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
@@ -1295,10 +1333,13 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
   }
 
   for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
-    if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
-      O << getRegisterName(Reg) << LayoutSuffix;
-    else
-      O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
+    if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg)) {
+      printRegName(O, Reg);
+      O << LayoutSuffix;
+    } else {
+      printRegName(O, Reg, AArch64::vreg);
+      O << LayoutSuffix;
+    }
 
     if (i + 1 != NumRegs)
       O << ", ";
@@ -1492,7 +1533,7 @@ void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
   }
 
   unsigned Reg = MI->getOperand(OpNum).getReg();
-  O << getRegisterName(Reg);
+  printRegName(O, Reg);
   if (suffix != 0)
     O << '.' << suffix;
 }
@@ -1574,7 +1615,7 @@ void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
     llvm_unreachable("Unsupported width");
   }
   unsigned Reg = MI->getOperand(OpNum).getReg();
-  O << getRegisterName(Reg - AArch64::Z0 + Base);
+  printRegName(O, Reg - AArch64::Z0 + Base);
 }
 
 template <unsigned ImmIs0, unsigned ImmIs1>
@@ -1591,5 +1632,5 @@ void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   unsigned Reg = MI->getOperand(OpNum).getReg();
-  O << getRegisterName(getWRegFromXReg(Reg));
+  printRegName(O, getWRegFromXReg(Reg));
 }
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
index 993f379b5343..c2afa240a391 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
@@ -28,6 +28,7 @@ class AArch64InstPrinter : public MCInstPrinter {
   void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
                  const MCSubtargetInfo &STI, raw_ostream &O) override;
   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
+  void printRegName(raw_ostream &OS, unsigned RegNo, unsigned AltIdx) const;
 
   // Autogenerated by tblgen.
   virtual void printInstruction(const MCInst *MI, uint64_t Address,

From af9c43590bcb0827b2e0a3c0ab1371c1bc064c2b Mon Sep 17 00:00:00 2001
From: Alain Carlucci <alain@rev.ng>
Date: Thu, 26 Nov 2020 16:55:50 +0100
Subject: [PATCH 2/5] InstPrinter: Add AArch64 immediate markup

---
 .../MCTargetDesc/AArch64InstPrinter.cpp       | 115 +++++++++++-------
 1 file changed, 70 insertions(+), 45 deletions(-)

diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 7b34fdee2af2..3c5dd5d47436 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -152,7 +152,7 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
         printRegName(O, Op0.getReg());
         O << ", ";
         printRegName(O, Op1.getReg());
-        O << ", #" << shift;
+        O << ", " << markup("<imm:") << "#" << shift << markup(">");
         printAnnotation(O, Annot);
         return;
       }
@@ -164,8 +164,9 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
       printRegName(O, Op0.getReg());
       O << ", ";
       printRegName(O, Op1.getReg());
-      O << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #"
-        << Op3.getImm() + 1;
+      O << ", " << markup("<imm:") << "#" << (Is64Bit ? 64 : 32) - Op2.getImm()
+        << markup(">") << ", " << markup("<imm:") << "#"
+        << Op3.getImm() + 1 << markup(">");
       printAnnotation(O, Annot);
       return;
     }
@@ -175,7 +176,9 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
     printRegName(O, Op0.getReg());
     O << ", ";
     printRegName(O, Op1.getReg());
-    O << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
+    O << ", " << markup("<imm:") << "#" << Op2.getImm() << markup(">")
+      << ", " << markup("<imm:") << "#" << Op3.getImm() - Op2.getImm() + 1
+      << markup(">");
     printAnnotation(O, Annot);
     return;
   }
@@ -196,7 +199,8 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
 
       O << "\tbfc\t";
       printRegName(O, Op0.getReg());
-      O << ", #" << LSB << ", #" << Width;
+      O << ", " << markup("<imm:") << "#" << LSB << markup(">")
+        << ", " << markup("<imm:") << "#" << Width << markup(">");
       printAnnotation(O, Annot);
       return;
     } else if (ImmS < ImmR) {
@@ -209,7 +213,8 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
       printRegName(O, Op0.getReg());
       O << ", ";
       printRegName(O, Op2.getReg());
-      O << ", #" << LSB << ", #" << Width;
+      O << ", " << markup("<imm:") << "#" << LSB << markup(">")
+        << ", " << markup("<imm:") << "#" << Width << markup(">");
       printAnnotation(O, Annot);
       return;
     }
@@ -221,7 +226,8 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
     printRegName(O, Op0.getReg());
     O << ", ";
     printRegName(O, Op2.getReg());
-    O << ", #" << LSB << ", #" << Width;
+    O << ", " << markup("<imm:") << "#" << LSB << markup(">")
+      << ", " << markup("<imm:") << "#" << Width << markup(">");
     printAnnotation(O, Annot);
     return;
   }
@@ -238,8 +244,9 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
       O << "\tmovn\t";
 
     printRegName(O, MI->getOperand(0).getReg());
-    O << ", #";
+    O << ", " << markup("<imm:") << "#";
     MI->getOperand(1).getExpr()->print(O, &MAI);
+    O << markup(">");
     return;
   }
 
@@ -247,8 +254,9 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
       MI->getOperand(2).isExpr()) {
     O << "\tmovk\t";
     printRegName(O, MI->getOperand(0).getReg());
-    O << ", #";
+    O << ", " << markup("<imm:") << "#";
     MI->getOperand(2).getExpr()->print(O, &MAI);
+    O << markup(">");
     return;
   }
 
@@ -267,7 +275,8 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                    Opcode == AArch64::MOVZXi ? 64 : 32)) {
       O << "\tmov\t";
       printRegName(O, MI->getOperand(0).getReg());
-      O << ", #" << formatImm(SignExtend64(Value, RegWidth));
+      O << ", " << markup("<imm:") << "#"
+        << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
       return;
     }
   }
@@ -283,7 +292,8 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
     if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
       O << "\tmov\t";
       printRegName(O, MI->getOperand(0).getReg());
-      O << ", #" << formatImm(SignExtend64(Value, RegWidth));
+      O << ", " << markup("<imm:") << "#"
+        << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
       return;
     }
   }
@@ -298,7 +308,8 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
     if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
       O << "\tmov\t";
       printRegName(O, MI->getOperand(0).getReg());
-      O << ", #" << formatImm(SignExtend64(Value, RegWidth));
+      O << ", " << markup("<imm:") << "#"
+        << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
       return;
     }
   }
@@ -778,7 +789,8 @@ void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
         printRegName(O, Reg);
       } else {
         assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
-        O << ", #" << LdStDesc->NaturalOffset;
+        O << ", " << markup("<imm:") << "#"
+          << LdStDesc->NaturalOffset << markup(">");
       }
     }
 
@@ -923,14 +935,14 @@ void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
-  O << "#" << formatImm(Op.getImm());
+  O << markup("<imm:") << "#" << formatImm(Op.getImm()) << markup(">");
 }
 
 void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
-  O << format("#%#llx", Op.getImm());
+  O << markup("<imm:") << format("#%#llx", Op.getImm()) << markup(">");
 }
 
 void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
@@ -939,7 +951,7 @@ void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
   if (Op.isReg()) {
     unsigned Reg = Op.getReg();
     if (Reg == AArch64::XZR)
-      O << "#" << Imm;
+      O << markup("<imm:") << "#" << Imm << markup(">");
     else
       printRegName(O, Reg);
   } else
@@ -972,7 +984,7 @@ void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
     assert(Val == MO.getImm() && "Add/sub immediate out of range!");
     unsigned Shift =
         AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
-    O << '#' << formatImm(Val);
+    O << markup("<imm:") << '#' << formatImm(Val) << markup(">");
     if (Shift != 0)
       printShifter(MI, OpNum + 1, STI, O);
 
@@ -990,8 +1002,9 @@ void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
                                          const MCSubtargetInfo &STI,
                                          raw_ostream &O) {
   uint64_t Val = MI->getOperand(OpNum).getImm();
-  O << "#0x";
+  O << markup("<imm:") << "#0x";
   O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
+  O << markup(">");
 }
 
 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
@@ -1003,7 +1016,8 @@ void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
       AArch64_AM::getShiftValue(Val) == 0)
     return;
   O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
-    << " #" << AArch64_AM::getShiftValue(Val);
+    << " " << markup("<imm:") << "#" << AArch64_AM::getShiftValue(Val)
+    << markup(">");
 }
 
 void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
@@ -1038,18 +1052,18 @@ void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
          ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
           ExtType == AArch64_AM::UXTW) ) {
       if (ShiftVal != 0)
-        O << ", lsl #" << ShiftVal;
+        O << ", lsl " << markup("<imm:") << "#" << ShiftVal << markup(">");
       return;
     }
   }
   O << ", " << AArch64_AM::getShiftExtendName(ExtType);
   if (ShiftVal != 0)
-    O << " #" << ShiftVal;
+    O << " " << markup("<imm:") << "#" << ShiftVal << markup(">");
 }
 
 static void printMemExtendImpl(bool SignExtend, bool DoShift,
                                unsigned Width, char SrcRegKind,
-                               raw_ostream &O) {
+                               raw_ostream &O, bool UseMarkup) {
   // sxtw, sxtx, uxtw or lsl (== uxtx)
   bool IsLSL = !SignExtend && SrcRegKind == 'x';
   if (IsLSL)
@@ -1057,8 +1071,14 @@ static void printMemExtendImpl(bool SignExtend, bool DoShift,
   else
     O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
 
-  if (DoShift || IsLSL)
-    O << " #" << Log2_32(Width / 8);
+  if (DoShift || IsLSL) {
+    O << " ";
+    if (UseMarkup)
+      O << "<imm:";
+    O << "#" << Log2_32(Width / 8);
+    if (UseMarkup)
+      O << ">";
+  }
 }
 
 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
@@ -1066,7 +1086,7 @@ void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
                                         unsigned Width) {
   bool SignExtend = MI->getOperand(OpNum).getImm();
   bool DoShift = MI->getOperand(OpNum + 1).getImm();
-  printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
+  printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O, UseMarkup);
 }
 
 template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
@@ -1083,7 +1103,7 @@ void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
   bool DoShift = ExtWidth != 8;
   if (SignExtend || DoShift || SrcRegKind == 'w') {
     O << ", ";
-    printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
+    printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O, UseMarkup);
   }
 }
 
@@ -1113,14 +1133,16 @@ template<int Scale>
 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
                                        const MCSubtargetInfo &STI,
                                        raw_ostream &O) {
-  O << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
+  O << markup("<imm:") << '#'
+    << formatImm(Scale * MI->getOperand(OpNum).getImm()) << markup(">");
 }
 
 void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
                                            unsigned Scale, raw_ostream &O) {
   const MCOperand MO = MI->getOperand(OpNum);
   if (MO.isImm()) {
-    O << "#" << formatImm(MO.getImm() * Scale);
+    O << markup("<imm:") << "#" << formatImm(MO.getImm() * Scale)
+      << markup(">");
   } else {
     assert(MO.isExpr() && "Unexpected operand type!");
     MO.getExpr()->print(O, &MAI);
@@ -1133,7 +1155,8 @@ void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
   O << '[';
   printRegName(O, MI->getOperand(OpNum).getReg());
   if (MO1.isImm()) {
-      O << ", #" << formatImm(MO1.getImm() * Scale);
+      O << ", " << markup("<imm:") << "#" << formatImm(MO1.getImm() * Scale)
+        << markup(">");
   } else {
     assert(MO1.isExpr() && "Unexpected operand type!");
     O << ", ";
@@ -1157,7 +1180,7 @@ void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
     return;
   }
 
-  O << '#' << formatImm(prfop);
+  O << markup("<imm:") << '#' << formatImm(prfop) << markup(">");
 }
 
 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
@@ -1168,7 +1191,7 @@ void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
   if (PSB)
     O << PSB->Name;
   else
-    O << '#' << formatImm(psbhintop);
+    O << markup("<imm:") << '#' << formatImm(psbhintop) << markup(">");
 }
 
 void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
@@ -1179,7 +1202,7 @@ void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
   if (BTI)
     O << BTI->Name;
   else
-    O << '#' << formatImm(btihintop);
+    O << markup("<imm:") << '#' << formatImm(btihintop) << markup(">");
 }
 
 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
@@ -1190,7 +1213,7 @@ void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
       MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm());
 
   // 8 decimal places are enough to perfectly represent permitted floats.
-  O << format("#%.8f", FPImm);
+  O << markup("<imm:") << format("#%.8f", FPImm) << markup(">");
 }
 
 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
@@ -1383,7 +1406,7 @@ void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum,
   // If the label has already been resolved to an immediate offset (say, when
   // we're running the disassembler), just print the immediate.
   if (Op.isImm()) {
-    O << "#" << formatImm(Op.getImm() * 4);
+    O << markup("<imm:") << "#" << formatImm(Op.getImm() * 4) << markup(">");
     return;
   }
 
@@ -1408,7 +1431,8 @@ void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
   // If the label has already been resolved to an immediate offset (say, when
   // we're running the disassembler), just print the immediate.
   if (Op.isImm()) {
-    O << "#" << formatImm(Op.getImm() * (1 << 12));
+    O << markup("<imm:") << "#" << formatImm(Op.getImm() * (1 << 12))
+      << markup(">");
     return;
   }
 
@@ -1436,7 +1460,7 @@ void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
   if (!Name.empty())
     O << Name;
   else
-    O << "#" << Val;
+    O << markup("<imm:") << "#" << Val << markup(">");
 }
 
 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
@@ -1488,7 +1512,7 @@ void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
   if (PState && PState->haveFeatures(STI.getFeatureBits()))
     O << PState->Name;
   else
-    O << "#" << formatImm(Val);
+    O << markup("<imm:") << "#" << formatImm(Val) << markup(">");
 }
 
 void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
@@ -1496,7 +1520,7 @@ void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
                                                 raw_ostream &O) {
   unsigned RawVal = MI->getOperand(OpNo).getImm();
   uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
-  O << format("#%#016llx", Val);
+  O << markup("<imm:") << format("#%#016llx", Val) << markup(">");
 }
 
 template<int64_t Angle, int64_t Remainder>
@@ -1504,7 +1528,7 @@ void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
                                                 const MCSubtargetInfo &STI,
                                                 raw_ostream &O) {
   unsigned Val = MI->getOperand(OpNo).getImm();
-  O << "#" << (Val * Angle) + Remainder;
+  O << markup("<imm:") << "#" << (Val * Angle) + Remainder << markup(">");
 }
 
 void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
@@ -1514,7 +1538,7 @@ void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
   if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
     O << Pat->Name;
   else
-    O << '#' << formatImm(Val);
+    O << markup("<imm:") << '#' << formatImm(Val) << markup(">");
 }
 
 template <char suffix>
@@ -1543,9 +1567,9 @@ void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) {
   typename std::make_unsigned<T>::type HexValue = Value;
 
   if (getPrintImmHex())
-    O << '#' << formatHex((uint64_t)HexValue);
+    O << markup("<imm:") << '#' << formatHex((uint64_t)HexValue) << markup(">");
   else
-    O << '#' << formatDec(Value);
+    O << markup("<imm:") << '#' << formatDec(Value) << markup(">");
 
   if (CommentStream) {
     // Do the opposite to that used for instruction operands.
@@ -1567,7 +1591,7 @@ void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
 
   // #0 lsl #8 is never pretty printed
   if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
-    O << '#' << formatImm(UnscaledVal);
+    O << markup("<imm:") << '#' << formatImm(UnscaledVal) << markup(">");
     printShifter(MI, OpNum + 1, STI, O);
     return;
   }
@@ -1597,7 +1621,7 @@ void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
   else if ((uint16_t)PrintVal == PrintVal)
     printImmSVE(PrintVal, O);
   else
-    O << '#' << formatHex((uint64_t)PrintVal);
+    O << markup("<imm:") << '#' << formatHex((uint64_t)PrintVal) << markup(">");
 }
 
 template <int Width>
@@ -1625,7 +1649,8 @@ void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
   auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
   auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
   unsigned Val = MI->getOperand(OpNum).getImm();
-  O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
+  O << markup("<imm:") << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr)
+    << markup(">");
 }
 
 void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,

From fea94efeafc8041c1483e12050468f10a901aeeb Mon Sep 17 00:00:00 2001
From: Alain Carlucci <alain@rev.ng>
Date: Thu, 26 Nov 2020 19:06:21 +0100
Subject: [PATCH 3/5] InstPrinter: Add SystemZ markup

---
 .../MCTargetDesc/SystemZInstPrinter.cpp       | 95 +++++++++++++------
 .../SystemZ/MCTargetDesc/SystemZInstPrinter.h |  4 +-
 llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp |  5 +-
 3 files changed, 70 insertions(+), 34 deletions(-)

diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
index 5893b227c08c..fcbed20eb602 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
@@ -24,32 +24,55 @@ using namespace llvm;
 #include "SystemZGenAsmWriter.inc"
 
 void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp,
-                                      unsigned Index, raw_ostream &O) {
+                                      unsigned Index, raw_ostream &O,
+                                      bool UseMarkup) {
+  if (UseMarkup)
+    O << "<imm:";
   O << Disp;
+  if (UseMarkup)
+    O << ">";
   if (Base || Index) {
     O << '(';
     if (Index) {
+      if (UseMarkup)
+        O << "<reg:";
       O << '%' << getRegisterName(Index);
+      if (UseMarkup)
+        O << ">";
       if (Base)
         O << ',';
     }
-    if (Base)
+    if (Base) {
+      if (UseMarkup)
+        O << "<reg:";
       O << '%' << getRegisterName(Base);
+      if (UseMarkup)
+        O << ">";
+    }
     O << ')';
   }
 }
 
 void SystemZInstPrinter::printOperand(const MCOperand &MO, const MCAsmInfo *MAI,
-                                      raw_ostream &O) {
+                                      raw_ostream &O, bool UseMarkup) {
   if (MO.isReg()) {
     if (!MO.getReg())
       O << '0';
-    else
+    else {
+      if (UseMarkup)
+        O << "<reg:";
       O << '%' << getRegisterName(MO.getReg());
+      if (UseMarkup)
+        O << ">";
+    }
   }
-  else if (MO.isImm())
+  else if (MO.isImm()) {
+    if (UseMarkup)
+      O << "<reg:";
     O << MO.getImm();
-  else if (MO.isExpr())
+    if (UseMarkup)
+      O << ">";
+  } else if (MO.isExpr())
     MO.getExpr()->print(O, MAI);
   else
     llvm_unreachable("Invalid operand");
@@ -63,94 +86,105 @@ void SystemZInstPrinter::printInst(const MCInst *MI, uint64_t Address,
 }
 
 void SystemZInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
-  O << '%' << getRegisterName(RegNo);
+  O << markup("<reg:") << '%' << getRegisterName(RegNo) << markup(">");
 }
 
 template <unsigned N>
-static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {
+static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O,
+                             bool UseMarkup) {
   int64_t Value = MI->getOperand(OpNum).getImm();
   assert(isUInt<N>(Value) && "Invalid uimm argument");
+  if (UseMarkup)
+    O << "<imm:";
   O << Value;
+  if (UseMarkup)
+    O << ">";
 }
 
 template <unsigned N>
-static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {
+static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O,
+                             bool UseMarkup) {
   int64_t Value = MI->getOperand(OpNum).getImm();
   assert(isInt<N>(Value) && "Invalid simm argument");
+  if (UseMarkup)
+    O << "<imm:";
   O << Value;
+  if (UseMarkup)
+    O << ">";
 }
 
 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
-  printUImmOperand<1>(MI, OpNum, O);
+  printUImmOperand<1>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
-  printUImmOperand<2>(MI, OpNum, O);
+  printUImmOperand<2>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printU3ImmOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
-  printUImmOperand<3>(MI, OpNum, O);
+  printUImmOperand<3>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printU4ImmOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
-  printUImmOperand<4>(MI, OpNum, O);
+  printUImmOperand<4>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printU6ImmOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
-  printUImmOperand<6>(MI, OpNum, O);
+  printUImmOperand<6>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printS8ImmOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
-  printSImmOperand<8>(MI, OpNum, O);
+  printSImmOperand<8>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printU8ImmOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
-  printUImmOperand<8>(MI, OpNum, O);
+  printUImmOperand<8>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printU12ImmOperand(const MCInst *MI, int OpNum,
                                             raw_ostream &O) {
-  printUImmOperand<12>(MI, OpNum, O);
+  printUImmOperand<12>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printS16ImmOperand(const MCInst *MI, int OpNum,
                                             raw_ostream &O) {
-  printSImmOperand<16>(MI, OpNum, O);
+  printSImmOperand<16>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printU16ImmOperand(const MCInst *MI, int OpNum,
                                             raw_ostream &O) {
-  printUImmOperand<16>(MI, OpNum, O);
+  printUImmOperand<16>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printS32ImmOperand(const MCInst *MI, int OpNum,
                                             raw_ostream &O) {
-  printSImmOperand<32>(MI, OpNum, O);
+  printSImmOperand<32>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printU32ImmOperand(const MCInst *MI, int OpNum,
                                             raw_ostream &O) {
-  printUImmOperand<32>(MI, OpNum, O);
+  printUImmOperand<32>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printU48ImmOperand(const MCInst *MI, int OpNum,
                                             raw_ostream &O) {
-  printUImmOperand<48>(MI, OpNum, O);
+  printUImmOperand<48>(MI, OpNum, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printPCRelOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
   const MCOperand &MO = MI->getOperand(OpNum);
   if (MO.isImm()) {
-    O << "0x";
+    O << markup("<imm:") << "0x";
     O.write_hex(MO.getImm());
+    O << markup(">");
   } else
     MO.getExpr()->print(O, &MAI);
 }
@@ -180,20 +214,20 @@ void SystemZInstPrinter::printPCRelTLSOperand(const MCInst *MI, int OpNum,
 
 void SystemZInstPrinter::printOperand(const MCInst *MI, int OpNum,
                                       raw_ostream &O) {
-  printOperand(MI->getOperand(OpNum), &MAI, O);
+  printOperand(MI->getOperand(OpNum), &MAI, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printBDAddrOperand(const MCInst *MI, int OpNum,
                                             raw_ostream &O) {
   printAddress(MI->getOperand(OpNum).getReg(),
-               MI->getOperand(OpNum + 1).getImm(), 0, O);
+               MI->getOperand(OpNum + 1).getImm(), 0, O, UseMarkup);
 }
 
 void SystemZInstPrinter::printBDXAddrOperand(const MCInst *MI, int OpNum,
                                              raw_ostream &O) {
   printAddress(MI->getOperand(OpNum).getReg(),
                MI->getOperand(OpNum + 1).getImm(),
-               MI->getOperand(OpNum + 2).getReg(), O);
+               MI->getOperand(OpNum + 2).getReg(), O, UseMarkup);
 }
 
 void SystemZInstPrinter::printBDLAddrOperand(const MCInst *MI, int OpNum,
@@ -203,7 +237,7 @@ void SystemZInstPrinter::printBDLAddrOperand(const MCInst *MI, int OpNum,
   uint64_t Length = MI->getOperand(OpNum + 2).getImm();
   O << Disp << '(' << Length;
   if (Base)
-    O << ",%" << getRegisterName(Base);
+    O << "," << markup("<reg:") << "%" << getRegisterName(Base) << markup(">");
   O << ')';
 }
 
@@ -212,9 +246,10 @@ void SystemZInstPrinter::printBDRAddrOperand(const MCInst *MI, int OpNum,
   unsigned Base = MI->getOperand(OpNum).getReg();
   uint64_t Disp = MI->getOperand(OpNum + 1).getImm();
   unsigned Length = MI->getOperand(OpNum + 2).getReg();
-  O << Disp << "(%" << getRegisterName(Length);
+  O << Disp << "(" << markup("<reg:") << "%" << getRegisterName(Length) 
+    << markup(">");
   if (Base)
-    O << ",%" << getRegisterName(Base);
+    O << "," << markup("<reg:") << "%" << getRegisterName(Base) << markup(">");
   O << ')';
 }
 
@@ -222,7 +257,7 @@ void SystemZInstPrinter::printBDVAddrOperand(const MCInst *MI, int OpNum,
                                              raw_ostream &O) {
   printAddress(MI->getOperand(OpNum).getReg(),
                MI->getOperand(OpNum + 1).getImm(),
-               MI->getOperand(OpNum + 2).getReg(), O);
+               MI->getOperand(OpNum + 2).getReg(), O, UseMarkup);
 }
 
 void SystemZInstPrinter::printCond4Operand(const MCInst *MI, int OpNum,
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h
index 5628e9252f03..a63efcf94aa7 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h
@@ -32,11 +32,11 @@ class SystemZInstPrinter : public MCInstPrinter {
 
   // Print an address with the given base, displacement and index.
   static void printAddress(unsigned Base, int64_t Disp, unsigned Index,
-                           raw_ostream &O);
+                           raw_ostream &O, bool UseMarkup);
 
   // Print the given operand.
   static void printOperand(const MCOperand &MO, const MCAsmInfo *MAI,
-                           raw_ostream &O);
+                           raw_ostream &O, bool UseMarkup);
 
   // Override MCInstPrinter.
   void printRegName(raw_ostream &O, unsigned RegNo) const override;
diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
index 67c4aa08f90d..9b95c0724c58 100644
--- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -705,7 +705,7 @@ bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
     return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
   SystemZMCInstLower Lower(MF->getContext(), *this);
   MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo)));
-  SystemZInstPrinter::printOperand(MO, MAI, OS);
+  SystemZInstPrinter::printOperand(MO, MAI, OS, false);
   return false;
 }
 
@@ -715,7 +715,8 @@ bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
                                               raw_ostream &OS) {
   SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),
                                    MI->getOperand(OpNo + 1).getImm(),
-                                   MI->getOperand(OpNo + 2).getReg(), OS);
+                                   MI->getOperand(OpNo + 2).getReg(), OS,
+                                   false);
   return false;
 }
 

From 87d69f0745e0f9d43d0bc756b56af27382386d3e Mon Sep 17 00:00:00 2001
From: Alain Carlucci <alain@rev.ng>
Date: Fri, 27 Nov 2020 14:19:44 +0100
Subject: [PATCH 4/5] InstPrinter: Add MIPS markup

---
 llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
index 649ba20324bf..89ed89fedea4 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
@@ -72,7 +72,8 @@ const char* Mips::MipsFCCToString(Mips::CondCode CC) {
 }
 
 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
-  OS << '$' << StringRef(getRegisterName(RegNo)).lower();
+  OS << markup("<reg:") << '$' << StringRef(getRegisterName(RegNo)).lower()
+     << markup(">");
 }
 
 void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address,
@@ -131,7 +132,7 @@ void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   }
 
   if (Op.isImm()) {
-    O << formatImm(Op.getImm());
+    O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
     return;
   }
 
@@ -147,7 +148,7 @@ void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
     Imm -= Offset;
     Imm &= (1 << Bits) - 1;
     Imm += Offset;
-    O << formatImm(Imm);
+    O << markup("<imm:") << formatImm(Imm) << markup(">");
     return;
   }
 
@@ -175,10 +176,12 @@ printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
     break;
   }
 
+  O << markup("<mem:");
   printOperand(MI, opNum+1, O);
   O << "(";
   printOperand(MI, opNum, O);
   O << ")";
+  O << markup(">");
 }
 
 void MipsInstPrinter::

From 6ae96a6e0967e771acec371bad4d2bab2fdd0348 Mon Sep 17 00:00:00 2001
From: Alain Carlucci <alain@rev.ng>
Date: Mon, 14 Dec 2020 15:36:12 +0100
Subject: [PATCH 5/5] InstPrinter: Improve X86 markup

---
 .../X86/MCTargetDesc/X86InstPrinterCommon.cpp |  4 +--
 .../X86/MCTargetDesc/X86IntelInstPrinter.cpp  | 27 ++++++++++---------
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
index a21555076976..3cdc48994e69 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
@@ -295,7 +295,7 @@ void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo,
                                          raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isImm())
-    O << formatImm(Op.getImm());
+    O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
   else {
     assert(Op.isExpr() && "unknown pcrel immediate operand");
     // If a symbolic branch target was added as a constant expression then print
@@ -303,7 +303,7 @@ void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo,
     const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
     int64_t Address;
     if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
-      O << formatHex((uint64_t)Address);
+      O << markup("<imm:") << formatHex((uint64_t)Address) << markup(">");
     } else {
       // Otherwise, just print the expression.
       Op.getExpr()->print(O, &MAI);
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
index f4bb0fbf62cd..d682c0c45da4 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
@@ -33,7 +33,7 @@ using namespace llvm;
 #include "X86GenAsmWriter1.inc"
 
 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
-  OS << getRegisterName(RegNo);
+  OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
 }
 
 void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
@@ -333,7 +333,7 @@ void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   if (Op.isReg()) {
     printRegName(O, Op.getReg());
   } else if (Op.isImm()) {
-    O << formatImm((int64_t)Op.getImm());
+    O << markup("<imm:") << formatImm((int64_t)Op.getImm()) << markup(">");
   } else {
     assert(Op.isExpr() && "unknown operand kind in printOperand");
     O << "offset ";
@@ -351,7 +351,7 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
 
-  O << '[';
+  O << markup("<mem:") << '[';
 
   bool NeedPlus = false;
   if (BaseReg.getReg()) {
@@ -382,28 +382,28 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
           DispVal = -DispVal;
         }
       }
-      O << formatImm(DispVal);
+      O << markup("<imm:") << formatImm(DispVal) << markup(">");
     }
   }
 
-  O << ']';
+  O << ']' << markup(">");
 }
 
 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
                                       raw_ostream &O) {
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + 1, O);
-  O << '[';
+  O << markup("<mem:") << '[';
   printOperand(MI, Op, O);
-  O << ']';
+  O << ']' << markup(">");
 }
 
 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
                                       raw_ostream &O) {
   // DI accesses are always ES-based.
-  O << "es:[";
+  O << "es:" << markup("<mem:") << '[';
   printOperand(MI, Op, O);
-  O << ']';
+  O << ']' << markup(">");
 }
 
 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
@@ -413,16 +413,16 @@ void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + 1, O);
 
-  O << '[';
+  O << markup("<mem:") << '[';
 
   if (DispSpec.isImm()) {
-    O << formatImm(DispSpec.getImm());
+    O << markup("<imm:") << formatImm(DispSpec.getImm()) << markup(">");
   } else {
     assert(DispSpec.isExpr() && "non-immediate displacement?");
     DispSpec.getExpr()->print(O, &MAI);
   }
 
-  O << ']';
+  O << ']' << markup(">");
 }
 
 void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
@@ -430,7 +430,8 @@ void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
   if (MI->getOperand(Op).isExpr())
     return MI->getOperand(Op).getExpr()->print(O, &MAI);
 
-  O << formatImm(MI->getOperand(Op).getImm() & 0xff);
+  O << markup("<imm:") << formatImm(MI->getOperand(Op).getImm() & 0xff)
+    << markup(">");
 }
 
 void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,