{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":268730905,"defaultBranch":"master","name":"qemu-upstream","ownerLogin":"revng","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2020-06-02T07:27:47.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/24596408?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1718790972.0","currentOid":""},"activityList":{"items":[{"before":"ec98dcc5ff8420c2d1430d1571b220cea99a2ba3","after":"a03addfc81783235e9b68e5aaf724a39221aecec","ref":"refs/heads/feature/xtensa-mb-libtcg","pushedAt":"2024-06-20T18:57:09.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"AntonJohansson","name":"Anton Johansson","path":"/AntonJohansson","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5958190?s=80&v=4"},"commit":{"message":"[TMP] xtensa, comment hw <-> target and disas -> target calls\n\nSigned-off-by: Anton Johansson ","shortMessageHtmlLink":"[TMP] xtensa, comment hw <-> target and disas -> target calls"}},{"before":null,"after":"ec98dcc5ff8420c2d1430d1571b220cea99a2ba3","ref":"refs/heads/feature/xtensa-mb-libtcg","pushedAt":"2024-06-19T09:56:12.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AntonJohansson","name":"Anton Johansson","path":"/AntonJohansson","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5958190?s=80&v=4"},"commit":{"message":"[TMP] xtensa, comment hw <-> target and disas -> target calls\n\nSigned-off-by: Anton Johansson ","shortMessageHtmlLink":"[TMP] xtensa, comment hw <-> target and disas -> target calls"}},{"before":"098870f8b7da7d6a6963782281577085aee929ce","after":"2c2f046d98f636c81e9222b445b0cb6027c31342","ref":"refs/heads/feature/heterogeneous-tcg","pushedAt":"2024-06-04T13:17:22.000Z","pushType":"push","commitsCount":8,"pusher":{"login":"AntonJohansson","name":"Anton Johansson","path":"/AntonJohansson","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5958190?s=80&v=4"},"commit":{"message":"accel/tcg: Make CPU_TLB_* target-inpendent\n\nThese are only used by accel/tcg and only for softmmu targets. Move\n*_MIN/*_DEFAULT to internal-common.h, and move *_MAX to a function that\nuses tcg_params->virt_addr_space_bits to compute the maximum.\n\nSigned-off-by: Anton Johansson ","shortMessageHtmlLink":"accel/tcg: Make CPU_TLB_* target-inpendent"}},{"before":"6ee2a384b0ee4dac68a7aa7e01f781c1475b8b54","after":"098870f8b7da7d6a6963782281577085aee929ce","ref":"refs/heads/feature/heterogeneous-tcg","pushedAt":"2024-05-31T12:42:31.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"AntonJohansson","name":"Anton Johansson","path":"/AntonJohansson","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5958190?s=80&v=4"},"commit":{"message":"target: Move TARGET_PAGE_BITS_MIN to TargetPageBits\n\nTARGET_PAGE_BITS_MIN is now defined as target_page.bits_min when\nPAGE_VARY is used, similar to other TARGET_PAGE_* macros. We still pick\nwhatever minimum the target specifies, however in a heterogeneous\ncontext we would want the maximum of all target_page.bits_min.\n\nThis also makes TLB_* macros target independent, and the static assert\nchecking for TLB_* flag overlap is moved to a runtime assert in\ntlb_init().\n\n[NOTE: I'm not happy with adding the TARGET_PAGE_BITS_MIN_SPECIFIC\nmacro, maybe we can remove it and use MachineClass->minimum_page_bits\n\nSigned-off-by: Anton Johansson ","shortMessageHtmlLink":"target: Move TARGET_PAGE_BITS_MIN to TargetPageBits"}},{"before":null,"after":"6ee2a384b0ee4dac68a7aa7e01f781c1475b8b54","ref":"refs/heads/feature/heterogeneous-tcg","pushedAt":"2024-05-30T22:07:11.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AntonJohansson","name":"Anton Johansson","path":"/AntonJohansson","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5958190?s=80&v=4"},"commit":{"message":"linux-user: Cast TARGET_PAGE_ALIGN() to size_t\n\nWhen TARGET_BITS_PAGE_VARY is set TARGET_PAGE_ALIGN() returns an int,\nmaking several comparisons of ELF_EF_DYN_BASE/TASK_UNMAPPED_BASE always\nevaluate to true.\n\nSigned-off-by: Anton Johansson ","shortMessageHtmlLink":"linux-user: Cast TARGET_PAGE_ALIGN() to size_t"}},{"before":null,"after":"9b3fdfbca851839a4b355fa68b99e72e401c330e","ref":"refs/heads/feature/helper-to-tcg","pushedAt":"2024-05-30T21:54:06.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AntonJohansson","name":"Anton Johansson","path":"/AntonJohansson","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5958190?s=80&v=4"},"commit":{"message":"helper-to-tcg: meson Remove hardcoded paths\n\nSigned-off-by: Anton Johansson ","shortMessageHtmlLink":"helper-to-tcg: meson Remove hardcoded paths"}},{"before":null,"after":"ce902719b95fd0989086656c5e08cd2af0dff9e1","ref":"refs/heads/feature/idef-parser","pushedAt":"2024-05-23T17:13:50.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AntonJohansson","name":"Anton Johansson","path":"/AntonJohansson","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5958190?s=80&v=4"},"commit":{"message":"target/hexagon: idef-parser simplify predicate init\n\nOnly predicate instruction arguments need to be initialized by\nidef-parser. This commit removes registers from the init_list and\nsimplifies gen_inst_init_args() slightly.\n\nSigned-off-by: Anton Johansson \nReviewed-by: Taylor Simpson \nReviewed-by: Brian Cain ","shortMessageHtmlLink":"target/hexagon: idef-parser simplify predicate init"}},{"before":"dd4b0de45965538f19bb40c7ddaaba384a8c613a","after":"7b68a5fe2fc5e9e03616ff8da9b385ae698cbf0a","ref":"refs/heads/master","pushedAt":"2024-05-23T17:08:38.000Z","pushType":"push","commitsCount":10000,"pusher":{"login":"AntonJohansson","name":"Anton Johansson","path":"/AntonJohansson","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5958190?s=80&v=4"},"commit":{"message":"Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging\n\n* hw/i386/pc_sysfw: Alias rather than copy isa-bios region\n* target/i386: add control bits support for LAM\n* target/i386: tweaks to new translator\n* target/i386: add support for LAM in CPUID enumeration\n* hw/i386/pc: Support smp.modules for x86 PC machine\n* target-i386: hyper-v: Correct kvm_hv_handle_exit return value\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmZOMlAUHHBib256aW5p\n# QHJlZGhhdC5jb20ACgkQv/vSX3jHroNTSwf8DOPgipepNcsxUQoV9nOBfNXqEWa6\n# DilQGwuu/3eMSPITUCGKVrtLR5azwCwvNfYYErVBPVIhjImnk3XHwfKpH1csadgq\n# 7Np8WGjAyKEIP/yC/K1VwsanFHv3hmC6jfcO3ZnsnlmbHsRINbvU9uMlFuiQkKJG\n# lP/dSUcTVhwLT6eFr9DVDUnq4Nh7j3saY85pZUoDclobpeRLaEAYrawha1/0uQpc\n# g7MZYsxT3sg9PIHlM+flpRvJNPz/ZDBdj4raN1xo4q0ET0KRLni6oEOVs5GpTY1R\n# t4O8a/IYkxeI15K9U7i0HwYI2wVwKZbHgp9XPMYVZFJdKBGT8bnF56pV9A==\n# =lp7q\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Wed 22 May 2024 10:58:40 AM PDT\n# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83\n# gpg: issuer \"pbonzini@redhat.com\"\n# gpg: Good signature from \"Paolo Bonzini \" [full]\n# gpg: aka \"Paolo Bonzini \" [full]\n\n* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (23 commits)\n target-i386: hyper-v: Correct kvm_hv_handle_exit return value\n i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14]\n i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4]\n i386: Add cache topology info in CPUCacheInfo\n hw/i386/pc: Support smp.modules for x86 PC machine\n tests: Add test case of APIC ID for module level parsing\n i386/cpu: Introduce module-id to X86CPU\n i386: Support module_id in X86CPUTopoIDs\n i386: Expose module level in CPUID[0x1F]\n i386: Support modules_per_die in X86CPUTopoInfo\n i386: Introduce module level cpu topology to CPUX86State\n i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level\n i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB]\n i386/cpu: Introduce bitmap to cache available CPU topology levels\n i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid()\n i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14]\n i386/cpu: Use APIC ID info to encode cache topo in CPUID[4]\n i386/cpu: Fix i/d-cache topology to core level for Intel CPU\n target/i386: add control bits support for LAM\n target/i386: add support for LAM in CPUID enumeration\n ...\n\nSigned-off-by: Richard Henderson ","shortMessageHtmlLink":"Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging"}},{"before":null,"after":"ad244a20170cc860c6c9dd3b22c12069eeab790a","ref":"refs/heads/feature/qemu-for-hqemu","pushedAt":"2023-07-28T12:10:23.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"aleclearmind","name":null,"path":"/aleclearmind","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2545644?s=80&v=4"},"commit":{"message":"Import HQEMU","shortMessageHtmlLink":"Import HQEMU"}},{"before":null,"after":"97e117fd117c99d9c57ef69a31488e173fa51dda","ref":"refs/heads/feature/zhangboyan-clean","pushedAt":"2023-07-28T12:09:08.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"aleclearmind","name":null,"path":"/aleclearmind","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2545644?s=80&v=4"},"commit":{"message":"Import zhangboyan","shortMessageHtmlLink":"Import zhangboyan"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEauWOlgA","startCursor":null,"endCursor":null}},"title":"Activity ยท revng/qemu-upstream"}