From 27e58b24b5735b611d9594baf7ab64b90d5cb544 Mon Sep 17 00:00:00 2001 From: Taichi Ishitani Date: Mon, 22 Jan 2024 10:34:01 +0900 Subject: [PATCH] redefine rws bit field type --- lib/rggen/systemverilog/ral.rb | 2 +- .../ral/bit_field/type/rwc_rwhw.rb | 5 - .../ral/bit_field/type/rwc_rwhw_rws.rb | 5 + lib/rggen/systemverilog/rtl.rb | 1 + .../systemverilog/rtl/bit_field/type/rws.erb | 20 + .../systemverilog/rtl/bit_field/type/rws.rb | 26 + .../ral/bit_field/type/rws_spec.rb | 29 + .../rtl/bit_field/type/rws_spec.rb | 562 ++++++++++++++++++ 8 files changed, 644 insertions(+), 6 deletions(-) delete mode 100644 lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw.rb create mode 100644 lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb create mode 100644 lib/rggen/systemverilog/rtl/bit_field/type/rws.erb create mode 100644 lib/rggen/systemverilog/rtl/bit_field/type/rws.rb create mode 100644 spec/rggen/systemverilog/ral/bit_field/type/rws_spec.rb create mode 100644 spec/rggen/systemverilog/rtl/bit_field/type/rws_spec.rb diff --git a/lib/rggen/systemverilog/ral.rb b/lib/rggen/systemverilog/ral.rb index 7e48932..6f5bd0d 100644 --- a/lib/rggen/systemverilog/ral.rb +++ b/lib/rggen/systemverilog/ral.rb @@ -27,7 +27,7 @@ 'ral/bit_field/type/rotrg_rwtrg_wotrg', 'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg', 'ral/bit_field/type/rowo_rowotrg', - 'ral/bit_field/type/rwc_rwhw', + 'ral/bit_field/type/rwc_rwhw_rws', 'ral/bit_field/type/rwe_rwl' ] end diff --git a/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw.rb b/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw.rb deleted file mode 100644 index 68cb3e2..0000000 --- a/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw.rb +++ /dev/null @@ -1,5 +0,0 @@ -# frozen_string_literal: true - -RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwhw]) do - sv_ral { access 'RW' } -end diff --git a/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb b/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb new file mode 100644 index 0000000..33fa876 --- /dev/null +++ b/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb @@ -0,0 +1,5 @@ +# frozen_string_literal: true + +RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwhw, :rws]) do + sv_ral { access 'RW' } +end diff --git a/lib/rggen/systemverilog/rtl.rb b/lib/rggen/systemverilog/rtl.rb index ed8487c..9ce97c8 100644 --- a/lib/rggen/systemverilog/rtl.rb +++ b/lib/rggen/systemverilog/rtl.rb @@ -46,6 +46,7 @@ 'rtl/bit_field/type/rwc', 'rtl/bit_field/type/rwe_rwl', 'rtl/bit_field/type/rwhw', + 'rtl/bit_field/type/rws', 'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc', 'rtl/bit_field/type/w0t_w1t', 'rtl/bit_field/type/w0trg_w1trg', diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb b/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb new file mode 100644 index 0000000..57458a3 --- /dev/null +++ b/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb @@ -0,0 +1,20 @@ +rggen_bit_field #( + .WIDTH (<%= width %>), + .INITIAL_VALUE (<%= initial_value %>), + .HW_SET_WIDTH (1) +) u_bit_field ( + .i_clk (<%= clock %>), + .i_rst_n (<%= reset %>), + .bit_field_if (<%= bit_field_if %>), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (<%= set_signal %>), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (<%= value_out[loop_variables] %>), + .o_value_unmasked () +); diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb new file mode 100644 index 0000000..c2ea8aa --- /dev/null +++ b/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb @@ -0,0 +1,26 @@ +# frozen_string_literal: true + +RgGen.define_list_item_feature(:bit_field, :type, :rws) do + sv_rtl do + build do + unless bit_field.reference? + input :set, { + name: "i_#{full_name}_set", width: 1, + array_size: array_size, array_format: array_port_format + } + end + output :value_out, { + name: "o_#{full_name}", width: width, + array_size: array_size, array_format: array_port_format + } + end + + main_code :bit_field, from_template: true + + private + + def set_signal + reference_bit_field || set[loop_variables] + end + end +end diff --git a/spec/rggen/systemverilog/ral/bit_field/type/rws_spec.rb b/spec/rggen/systemverilog/ral/bit_field/type/rws_spec.rb new file mode 100644 index 0000000..2c6bad9 --- /dev/null +++ b/spec/rggen/systemverilog/ral/bit_field/type/rws_spec.rb @@ -0,0 +1,29 @@ + +# frozen_string_literal: true + +RSpec.describe 'bit_field/type/rws' do + include_context 'clean-up builder' + include_context 'bit field ral common' + + before(:all) do + RgGen.enable(:bit_field, :type, [:rw, :rws]) + end + + specify 'アクセス属性はRW' do + sv_ral = create_sv_ral do + register do + name 'register_0' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rws; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1; type :rws; initial_value 0; reference 'register_1.bit_field_0' } + end + + register do + name 'register_1' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rw; initial_value 0 } + end + end + + expect(sv_ral.bit_fields[0].access).to eq 'RW' + expect(sv_ral.bit_fields[1].access).to eq 'RW' + end +end diff --git a/spec/rggen/systemverilog/rtl/bit_field/type/rws_spec.rb b/spec/rggen/systemverilog/rtl/bit_field/type/rws_spec.rb new file mode 100644 index 0000000..0cd17a9 --- /dev/null +++ b/spec/rggen/systemverilog/rtl/bit_field/type/rws_spec.rb @@ -0,0 +1,562 @@ + +# frozen_string_literal: true + +RSpec.describe 'bit_field/type/rws' do + include_context 'clean-up builder' + include_context 'bit field rtl common' + + before(:all) do + RgGen.enable(:bit_field, :type, [:rw, :rws]) + end + + let(:bit_fields) do + create_bit_fields do + byte_size 256 + + register do + name 'register_0' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rws; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rws; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rws; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rws; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rws; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rws; initial_value 0; reference 'register_4.bit_field_0' } + end + + register do + name 'register_1' + size [4] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rws; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rws; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rws; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rws; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rws; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rws; initial_value 0; reference 'register_4.bit_field_0' } + end + + register do + name 'register_2' + size [2, 2] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rws; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rws; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rws; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rws; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rws; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rws; initial_value 0; reference 'register_4.bit_field_0' } + end + + register_file do + name 'register_file_3' + size [2, 2] + register_file do + name 'register_file_0' + register do + name 'register_0' + size [2, 2] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rws; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rws; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rws; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rws; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rws; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rws; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } + end + end + end + + register do + name 'register_4' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rw; initial_value 0 } + end + + register_file do + name 'register_file_5' + size [2, 2] + register_file do + name 'register_file_0' + register do + name 'register_0' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rw; initial_value 0 } + end + end + end + end + end + + it '出力ポート#value_outを持つ' do + expect(bit_fields[0]).to have_port( + :register_block, :value_out, + name: 'o_register_0_bit_field_0', direction: :output, data_type: :logic, width: 1 + ) + expect(bit_fields[2]).to have_port( + :register_block, :value_out, + name: 'o_register_0_bit_field_2', direction: :output, data_type: :logic, width: 2 + ) + expect(bit_fields[4]).to have_port( + :register_block, :value_out, + name: 'o_register_0_bit_field_4', direction: :output, data_type: :logic, width: 4, + array_size: [2], array_format: array_port_format + ) + + expect(bit_fields[6]).to have_port( + :register_block, :value_out, + name: 'o_register_1_bit_field_0', direction: :output, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[8]).to have_port( + :register_block, :value_out, + name: 'o_register_1_bit_field_2', direction: :output, data_type: :logic, width: 2, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[10]).to have_port( + :register_block, :value_out, + name: 'o_register_1_bit_field_4', direction: :output, data_type: :logic, width: 4, + array_size: [4, 2], array_format: array_port_format + ) + + expect(bit_fields[12]).to have_port( + :register_block, :value_out, + name: 'o_register_2_bit_field_0', direction: :output, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[14]).to have_port( + :register_block, :value_out, + name: 'o_register_2_bit_field_2', direction: :output, data_type: :logic, width: 2, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[16]).to have_port( + :register_block, :value_out, + name: 'o_register_2_bit_field_4', direction: :output, data_type: :logic, width: 4, + array_size: [2, 2, 2], array_format: array_port_format + ) + + expect(bit_fields[18]).to have_port( + :register_block, :value_out, + name: 'o_register_file_3_register_file_0_register_0_bit_field_0', direction: :output, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[20]).to have_port( + :register_block, :value_out, + name: 'o_register_file_3_register_file_0_register_0_bit_field_2', direction: :output, data_type: :logic, width: 2, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[22]).to have_port( + :register_block, :value_out, + name: 'o_register_file_3_register_file_0_register_0_bit_field_4', direction: :output, data_type: :logic, width: 4, + array_size: [2, 2, 2, 2, 2], array_format: array_port_format + ) + end + + context '参照ビットフィールドを持たない場合' do + it '入力ポート#setを持つ' do + expect(bit_fields[0]).to have_port( + :register_block, :set, + name: 'i_register_0_bit_field_0_set', direction: :input, data_type: :logic, width: 1 + ) + expect(bit_fields[2]).to have_port( + :register_block, :set, + name: 'i_register_0_bit_field_2_set', direction: :input, data_type: :logic, width: 1 + ) + expect(bit_fields[4]).to have_port( + :register_block, :set, + name: 'i_register_0_bit_field_4_set', direction: :input, data_type: :logic, width: 1, + array_size: [2], array_format: array_port_format + ) + + expect(bit_fields[6]).to have_port( + :register_block, :set, + name: 'i_register_1_bit_field_0_set', direction: :input, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[8]).to have_port( + :register_block, :set, + name: 'i_register_1_bit_field_2_set', direction: :input, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[10]).to have_port( + :register_block, :set, + name: 'i_register_1_bit_field_4_set', direction: :input, data_type: :logic, width: 1, + array_size: [4, 2], array_format: array_port_format + ) + + expect(bit_fields[12]).to have_port( + :register_block, :set, + name: 'i_register_2_bit_field_0_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[14]).to have_port( + :register_block, :set, + name: 'i_register_2_bit_field_2_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[16]).to have_port( + :register_block, :set, + name: 'i_register_2_bit_field_4_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2], array_format: array_port_format + ) + + expect(bit_fields[18]).to have_port( + :register_block, :set, + name: 'i_register_file_3_register_file_0_register_0_bit_field_0_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[20]).to have_port( + :register_block, :set, + name: 'i_register_file_3_register_file_0_register_0_bit_field_2_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[22]).to have_port( + :register_block, :set, + name: 'i_register_file_3_register_file_0_register_0_bit_field_4_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2, 2], array_format: array_port_format + ) + end + end + + context '参照ビットフィールドを持つ場合' do + it '入力ポート#setを持たない' do + expect(bit_fields[1]).to not_have_port( + :register_block, :set, + name: 'i_register_0_bit_field_1_set', direction: :input, data_type: :logic, width: 1 + ) + expect(bit_fields[3]).to not_have_port( + :register_block, :set, + name: 'i_register_0_bit_field_3_set', direction: :input, data_type: :logic, width: 1 + ) + expect(bit_fields[5]).to not_have_port( + :register_block, :set, + name: 'i_register_0_bit_field_5_set', direction: :input, data_type: :logic, width: 1, + array_size: [2], array_format: array_port_format + ) + + expect(bit_fields[7]).to not_have_port( + :register_block, :set, + name: 'i_register_1_bit_field_1_set', direction: :input, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[9]).to not_have_port( + :register_block, :set, + name: 'i_register_1_bit_field_3_set', direction: :input, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[11]).to not_have_port( + :register_block, :set, + name: 'i_register_1_bit_field_5_set', direction: :input, data_type: :logic, width: 1, + array_size: [4, 2], array_format: array_port_format + ) + + expect(bit_fields[13]).to not_have_port( + :register_block, :set, + name: 'i_register_2_bit_field_1_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[15]).to not_have_port( + :register_block, :set, + name: 'i_register_2_bit_field_3_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[17]).to not_have_port( + :register_block, :set, + name: 'i_register_2_bit_field_5_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2], array_format: array_port_format + ) + + expect(bit_fields[19]).to not_have_port( + :register_block, :set, + name: 'i_register_file_3_register_file_0_register_0_bit_field_1_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[21]).to not_have_port( + :register_block, :set, + name: 'i_register_file_3_register_file_0_register_0_bit_field_3_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[23]).to not_have_port( + :register_block, :set, + name: 'i_register_file_3_register_file_0_register_0_bit_field_5_set', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2, 2], array_format: array_port_format + ) + end + end + + describe '#generate_code' do + let(:array_port_format) { :packed } + + it 'rggen_bit_fieldをインスタンスするコードを出力する' do + expect(bit_fields[0]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_0_bit_field_0_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_0), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[1]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_1), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[2]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_0_bit_field_2_set), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_2), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[3]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_3), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[4]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_0_bit_field_4_set[i]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_4[i]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[5]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_5[i]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[10]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_1_bit_field_4_set[i][j]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_1_bit_field_4[i][j]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[11]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_1_bit_field_5[i][j]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[16]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_2_bit_field_4_set[i][j][k]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_2_bit_field_4[i][j][k]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[17]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_2_bit_field_5[i][j][k]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[22]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_file_3_register_file_0_register_0_bit_field_4_set[i][j][k][l][m]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_3_register_file_0_register_0_bit_field_4[i][j][k][l][m]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[23]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[26+2*i+j].value[0+:1]), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_3_register_file_0_register_0_bit_field_5[i][j][k][l][m]), + .o_value_unmasked () + ); + CODE + end + end +end