diff --git a/lib/rggen/systemverilog/ral.rb b/lib/rggen/systemverilog/ral.rb index 0a087c9..6f5bd0d 100644 --- a/lib/rggen/systemverilog/ral.rb +++ b/lib/rggen/systemverilog/ral.rb @@ -23,11 +23,11 @@ 'ral/register/type/indirect', 'ral/bit_field/type', 'ral/bit_field/type/custom', - 'ral/bit_field/type/rof_rol', + 'ral/bit_field/type/rof_rohw', 'ral/bit_field/type/rotrg_rwtrg_wotrg', 'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg', 'ral/bit_field/type/rowo_rowotrg', - 'ral/bit_field/type/rwc_rws', + 'ral/bit_field/type/rwc_rwhw_rws', 'ral/bit_field/type/rwe_rwl' ] end diff --git a/lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb b/lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb new file mode 100644 index 0000000..58b3d29 --- /dev/null +++ b/lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb @@ -0,0 +1,5 @@ +# frozen_string_literal: true + +RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rohw]) do + sv_ral { access 'RO' } +end diff --git a/lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb b/lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb deleted file mode 100644 index ebc6e62..0000000 --- a/lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb +++ /dev/null @@ -1,5 +0,0 @@ -# frozen_string_literal: true - -RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rol]) do - sv_ral { access 'RO' } -end diff --git a/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb b/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb new file mode 100644 index 0000000..33fa876 --- /dev/null +++ b/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb @@ -0,0 +1,5 @@ +# frozen_string_literal: true + +RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwhw, :rws]) do + sv_ral { access 'RW' } +end diff --git a/lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb b/lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb deleted file mode 100644 index ce58e57..0000000 --- a/lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb +++ /dev/null @@ -1,5 +0,0 @@ -# frozen_string_literal: true - -RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rws]) do - sv_ral { access 'RW' } -end diff --git a/lib/rggen/systemverilog/rtl.rb b/lib/rggen/systemverilog/rtl.rb index d35018d..9ce97c8 100644 --- a/lib/rggen/systemverilog/rtl.rb +++ b/lib/rggen/systemverilog/rtl.rb @@ -38,13 +38,14 @@ 'rtl/bit_field/type/rc_w0c_w1c_wc_woc', 'rtl/bit_field/type/ro_rotrg', 'rtl/bit_field/type/rof', - 'rtl/bit_field/type/rol', + 'rtl/bit_field/type/rohw', 'rtl/bit_field/type/row0trg_row1trg', 'rtl/bit_field/type/rowo_rowotrg', 'rtl/bit_field/type/rs_w0s_w1s_ws_wos', 'rtl/bit_field/type/rw_rwtrg_w1', 'rtl/bit_field/type/rwc', 'rtl/bit_field/type/rwe_rwl', + 'rtl/bit_field/type/rwhw', 'rtl/bit_field/type/rws', 'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc', 'rtl/bit_field/type/w0t_w1t', diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rol.erb b/lib/rggen/systemverilog/rtl/bit_field/type/rohw.erb similarity index 93% rename from lib/rggen/systemverilog/rtl/bit_field/type/rol.erb rename to lib/rggen/systemverilog/rtl/bit_field/type/rohw.erb index daabbc4..4df241e 100644 --- a/lib/rggen/systemverilog/rtl/bit_field/type/rol.erb +++ b/lib/rggen/systemverilog/rtl/bit_field/type/rohw.erb @@ -9,7 +9,7 @@ rggen_bit_field #( .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (<%= latch_signal %>), + .i_hw_write_enable (<%= valid_signal %>), .i_hw_write_data (<%= value_in[loop_variables] %>), .i_hw_set ('0), .i_hw_clear ('0), diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rol.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb similarity index 72% rename from lib/rggen/systemverilog/rtl/bit_field/type/rol.rb rename to lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb index 845e40c..6c92f8e 100644 --- a/lib/rggen/systemverilog/rtl/bit_field/type/rol.rb +++ b/lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb @@ -1,11 +1,11 @@ # frozen_string_literal: true -RgGen.define_list_item_feature(:bit_field, :type, :rol) do +RgGen.define_list_item_feature(:bit_field, :type, :rohw) do sv_rtl do build do unless bit_field.reference? - input :latch, { - name: "i_#{full_name}_latch", width: 1, + input :valid, { + name: "i_#{full_name}_valid", width: 1, array_size: array_size, array_format: array_port_format } end @@ -23,8 +23,8 @@ private - def latch_signal - reference_bit_field || latch[loop_variables] + def valid_signal + reference_bit_field || valid[loop_variables] end end end diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb b/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb new file mode 100644 index 0000000..67a660a --- /dev/null +++ b/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb @@ -0,0 +1,19 @@ +rggen_bit_field #( + .WIDTH (<%= width %>), + .INITIAL_VALUE (<%= initial_value %>) +) u_bit_field ( + .i_clk (<%= clock %>), + .i_rst_n (<%= reset %>), + .bit_field_if (<%= bit_field_if %>), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (<%= valid_signal %>), + .i_hw_write_data (<%= value_in[loop_variables] %>), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (<%= value_out[loop_variables] %>), + .o_value_unmasked () +); diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb new file mode 100644 index 0000000..3721342 --- /dev/null +++ b/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb @@ -0,0 +1,30 @@ +# frozen_string_literal: true + +RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do + sv_rtl do + build do + unless bit_field.reference? + input :valid, { + name: "i_#{full_name}_valid", width: 1, + array_size: array_size, array_format: array_port_format + } + end + input :value_in, { + name: "i_#{full_name}", width: width, + array_size: array_size, array_format: array_port_format + } + output :value_out, { + name: "o_#{full_name}", width: width, + array_size: array_size, array_format: array_port_format + } + end + + main_code :bit_field, from_template: true + + private + + def valid_signal + reference_bit_field || valid[loop_variables] + end + end +end diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb b/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb index 18299d5..57458a3 100644 --- a/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +++ b/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb @@ -1,6 +1,7 @@ rggen_bit_field #( .WIDTH (<%= width %>), - .INITIAL_VALUE (<%= initial_value %>) + .INITIAL_VALUE (<%= initial_value %>), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (<%= clock %>), .i_rst_n (<%= reset %>), @@ -8,9 +9,9 @@ rggen_bit_field #( .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (<%= set_signal %>), - .i_hw_write_data (<%= value_in[loop_variables] %>), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (<%= set_signal %>), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), diff --git a/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb b/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb index bd72a81..c2ea8aa 100644 --- a/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +++ b/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb @@ -9,10 +9,6 @@ array_size: array_size, array_format: array_port_format } end - input :value_in, { - name: "i_#{full_name}", width: width, - array_size: array_size, array_format: array_port_format - } output :value_out, { name: "o_#{full_name}", width: width, array_size: array_size, array_format: array_port_format diff --git a/spec/rggen/systemverilog/ral/bit_field/type/rol_spec.rb b/spec/rggen/systemverilog/ral/bit_field/type/rohw_spec.rb similarity index 78% rename from spec/rggen/systemverilog/ral/bit_field/type/rol_spec.rb rename to spec/rggen/systemverilog/ral/bit_field/type/rohw_spec.rb index 92b9b7b..b43bd0d 100644 --- a/spec/rggen/systemverilog/ral/bit_field/type/rol_spec.rb +++ b/spec/rggen/systemverilog/ral/bit_field/type/rohw_spec.rb @@ -1,19 +1,19 @@ # frozen_string_literal: true -RSpec.describe 'bit_field/type/rwl' do +RSpec.describe 'bit_field/type/rohw' do include_context 'clean-up builder' include_context 'bit field ral common' before(:all) do - RgGen.enable(:bit_field, :type, [:rw, :rol]) + RgGen.enable(:bit_field, :type, [:rw, :rohw]) end specify 'アクセス属性はRO' do sv_ral = create_sv_ral do register do name 'register_0' - bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rol; initial_value 0 } - bit_field { name 'bit_field_1'; bit_assignment lsb: 1; type :rol; initial_value 0; reference 'register_1.bit_field_0' } + bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rohw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1; type :rohw; initial_value 0; reference 'register_1.bit_field_0' } end register do diff --git a/spec/rggen/systemverilog/ral/bit_field/type/rwhw_spec.rb b/spec/rggen/systemverilog/ral/bit_field/type/rwhw_spec.rb new file mode 100644 index 0000000..87627d1 --- /dev/null +++ b/spec/rggen/systemverilog/ral/bit_field/type/rwhw_spec.rb @@ -0,0 +1,29 @@ + +# frozen_string_literal: true + +RSpec.describe 'bit_field/type/rwhw' do + include_context 'clean-up builder' + include_context 'bit field ral common' + + before(:all) do + RgGen.enable(:bit_field, :type, [:rw, :rwhw]) + end + + specify 'アクセス属性はRW' do + sv_ral = create_sv_ral do + register do + name 'register_0' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1; type :rwhw; initial_value 0; reference 'register_1.bit_field_0' } + end + + register do + name 'register_1' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rw; initial_value 0 } + end + end + + expect(sv_ral.bit_fields[0].access).to eq 'RW' + expect(sv_ral.bit_fields[1].access).to eq 'RW' + end +end diff --git a/spec/rggen/systemverilog/rtl/bit_field/type/rol_spec.rb b/spec/rggen/systemverilog/rtl/bit_field/type/rohw_spec.rb similarity index 83% rename from spec/rggen/systemverilog/rtl/bit_field/type/rol_spec.rb rename to spec/rggen/systemverilog/rtl/bit_field/type/rohw_spec.rb index b9bb8e9..c4517d2 100644 --- a/spec/rggen/systemverilog/rtl/bit_field/type/rol_spec.rb +++ b/spec/rggen/systemverilog/rtl/bit_field/type/rohw_spec.rb @@ -1,12 +1,12 @@ # frozen_string_literal: true -RSpec.describe 'bit_field/type/rol' do +RSpec.describe 'bit_field/type/rohw' do include_context 'clean-up builder' include_context 'bit field rtl common' before(:all) do - RgGen.enable(:bit_field, :type, [:rw, :rol]) + RgGen.enable(:bit_field, :type, [:rw, :rohw]) end let(:bit_fields) do @@ -15,34 +15,34 @@ register do name 'register_0' - bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rol; initial_value 0 } - bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rol; initial_value 0; reference 'register_4.bit_field_0' } - bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rol; initial_value 0 } - bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rol; initial_value 0; reference 'register_4.bit_field_0' } - bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rol; initial_value 0 } - bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rol; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rohw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rohw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rohw; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rohw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rohw; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rohw; initial_value 0; reference 'register_4.bit_field_0' } end register do name 'register_1' size [4] - bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rol; initial_value 0 } - bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rol; initial_value 0; reference 'register_4.bit_field_0' } - bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rol; initial_value 0 } - bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rol; initial_value 0; reference 'register_4.bit_field_0' } - bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rol; initial_value 0 } - bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rol; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rohw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rohw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rohw; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rohw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rohw; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rohw; initial_value 0; reference 'register_4.bit_field_0' } end register do name 'register_2' size [2, 2] - bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rol; initial_value 0 } - bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rol; initial_value 0; reference 'register_4.bit_field_0' } - bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rol; initial_value 0 } - bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rol; initial_value 0; reference 'register_4.bit_field_0' } - bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rol; initial_value 0 } - bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rol; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rohw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rohw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rohw; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rohw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rohw; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rohw; initial_value 0; reference 'register_4.bit_field_0' } end register_file do @@ -53,12 +53,12 @@ register do name 'register_0' size [2, 2] - bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rol; initial_value 0 } - bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rol; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } - bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rol; initial_value 0 } - bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rol; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } - bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rol; initial_value 0 } - bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rol; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rohw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rohw; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rohw; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rohw; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rohw; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rohw; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } end end end @@ -213,132 +213,132 @@ end context '参照ビットフィールドを持たない場合' do - it '入力ポート#latchを持つ' do + it '入力ポート#validを持つ' do expect(bit_fields[0]).to have_port( - :register_block, :latch, - name: 'i_register_0_bit_field_0_latch', direction: :input, data_type: :logic, width: 1 + :register_block, :valid, + name: 'i_register_0_bit_field_0_valid', direction: :input, data_type: :logic, width: 1 ) expect(bit_fields[2]).to have_port( - :register_block, :latch, - name: 'i_register_0_bit_field_2_latch', direction: :input, data_type: :logic, width: 1 + :register_block, :valid, + name: 'i_register_0_bit_field_2_valid', direction: :input, data_type: :logic, width: 1 ) expect(bit_fields[4]).to have_port( - :register_block, :latch, - name: 'i_register_0_bit_field_4_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_0_bit_field_4_valid', direction: :input, data_type: :logic, width: 1, array_size: [2], array_format: array_port_format ) expect(bit_fields[6]).to have_port( - :register_block, :latch, - name: 'i_register_1_bit_field_0_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_1_bit_field_0_valid', direction: :input, data_type: :logic, width: 1, array_size: [4], array_format: array_port_format ) expect(bit_fields[8]).to have_port( - :register_block, :latch, - name: 'i_register_1_bit_field_2_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_1_bit_field_2_valid', direction: :input, data_type: :logic, width: 1, array_size: [4], array_format: array_port_format ) expect(bit_fields[10]).to have_port( - :register_block, :latch, - name: 'i_register_1_bit_field_4_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_1_bit_field_4_valid', direction: :input, data_type: :logic, width: 1, array_size: [4, 2], array_format: array_port_format ) expect(bit_fields[12]).to have_port( - :register_block, :latch, - name: 'i_register_2_bit_field_0_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_2_bit_field_0_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2], array_format: array_port_format ) expect(bit_fields[14]).to have_port( - :register_block, :latch, - name: 'i_register_2_bit_field_2_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_2_bit_field_2_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2], array_format: array_port_format ) expect(bit_fields[16]).to have_port( - :register_block, :latch, - name: 'i_register_2_bit_field_4_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_2_bit_field_4_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2, 2], array_format: array_port_format ) expect(bit_fields[18]).to have_port( - :register_block, :latch, - name: 'i_register_file_3_register_file_0_register_0_bit_field_0_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_0_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2, 2, 2], array_format: array_port_format ) expect(bit_fields[20]).to have_port( - :register_block, :latch, - name: 'i_register_file_3_register_file_0_register_0_bit_field_2_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_2_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2, 2, 2], array_format: array_port_format ) expect(bit_fields[22]).to have_port( - :register_block, :latch, - name: 'i_register_file_3_register_file_0_register_0_bit_field_4_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_4_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2, 2, 2, 2], array_format: array_port_format ) end end context '参照ビットフィールドを持つ場合' do - it '入力ポート#latchを持たない' do + it '入力ポート#validを持たない' do expect(bit_fields[1]).to not_have_port( - :register_block, :latch, - name: 'i_register_0_bit_field_1_latch', direction: :input, data_type: :logic, width: 1 + :register_block, :valid, + name: 'i_register_0_bit_field_1_valid', direction: :input, data_type: :logic, width: 1 ) expect(bit_fields[3]).to not_have_port( - :register_block, :latch, - name: 'i_register_0_bit_field_3_latch', direction: :input, data_type: :logic, width: 1 + :register_block, :valid, + name: 'i_register_0_bit_field_3_valid', direction: :input, data_type: :logic, width: 1 ) expect(bit_fields[5]).to not_have_port( - :register_block, :latch, - name: 'i_register_0_bit_field_5_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_0_bit_field_5_valid', direction: :input, data_type: :logic, width: 1, array_size: [2], array_format: array_port_format ) expect(bit_fields[7]).to not_have_port( - :register_block, :latch, - name: 'i_register_1_bit_field_1_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_1_bit_field_1_valid', direction: :input, data_type: :logic, width: 1, array_size: [4], array_format: array_port_format ) expect(bit_fields[9]).to not_have_port( - :register_block, :latch, - name: 'i_register_1_bit_field_3_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_1_bit_field_3_valid', direction: :input, data_type: :logic, width: 1, array_size: [4], array_format: array_port_format ) expect(bit_fields[11]).to not_have_port( - :register_block, :latch, - name: 'i_register_1_bit_field_5_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_1_bit_field_5_valid', direction: :input, data_type: :logic, width: 1, array_size: [4, 2], array_format: array_port_format ) expect(bit_fields[13]).to not_have_port( - :register_block, :latch, - name: 'i_register_2_bit_field_1_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_2_bit_field_1_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2], array_format: array_port_format ) expect(bit_fields[15]).to not_have_port( - :register_block, :latch, - name: 'i_register_2_bit_field_3_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_2_bit_field_3_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2], array_format: array_port_format ) expect(bit_fields[17]).to not_have_port( - :register_block, :latch, - name: 'i_register_2_bit_field_5_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_2_bit_field_5_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2, 2], array_format: array_port_format ) expect(bit_fields[19]).to not_have_port( - :register_block, :latch, - name: 'i_register_file_3_register_file_0_register_0_bit_field_1_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_1_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2, 2, 2], array_format: array_port_format ) expect(bit_fields[21]).to not_have_port( - :register_block, :latch, - name: 'i_register_file_3_register_file_0_register_0_bit_field_3_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_3_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2, 2, 2], array_format: array_port_format ) expect(bit_fields[23]).to not_have_port( - :register_block, :latch, - name: 'i_register_file_3_register_file_0_register_0_bit_field_5_latch', direction: :input, data_type: :logic, width: 1, + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_5_valid', direction: :input, data_type: :logic, width: 1, array_size: [2, 2, 2, 2, 2], array_format: array_port_format ) end @@ -360,7 +360,7 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_0_bit_field_0_latch), + .i_hw_write_enable (i_register_0_bit_field_0_valid), .i_hw_write_data (i_register_0_bit_field_0), .i_hw_set ('0), .i_hw_clear ('0), @@ -406,7 +406,7 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_0_bit_field_2_latch), + .i_hw_write_enable (i_register_0_bit_field_2_valid), .i_hw_write_data (i_register_0_bit_field_2), .i_hw_set ('0), .i_hw_clear ('0), @@ -452,7 +452,7 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_0_bit_field_4_latch[i]), + .i_hw_write_enable (i_register_0_bit_field_4_valid[i]), .i_hw_write_data (i_register_0_bit_field_4[i]), .i_hw_set ('0), .i_hw_clear ('0), @@ -498,7 +498,7 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_1_bit_field_4_latch[i][j]), + .i_hw_write_enable (i_register_1_bit_field_4_valid[i][j]), .i_hw_write_data (i_register_1_bit_field_4[i][j]), .i_hw_set ('0), .i_hw_clear ('0), @@ -544,7 +544,7 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_2_bit_field_4_latch[i][j][k]), + .i_hw_write_enable (i_register_2_bit_field_4_valid[i][j][k]), .i_hw_write_data (i_register_2_bit_field_4[i][j][k]), .i_hw_set ('0), .i_hw_clear ('0), @@ -590,7 +590,7 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_file_3_register_file_0_register_0_bit_field_4_latch[i][j][k][l][m]), + .i_hw_write_enable (i_register_file_3_register_file_0_register_0_bit_field_4_valid[i][j][k][l][m]), .i_hw_write_data (i_register_file_3_register_file_0_register_0_bit_field_4[i][j][k][l][m]), .i_hw_set ('0), .i_hw_clear ('0), diff --git a/spec/rggen/systemverilog/rtl/bit_field/type/rwhw_spec.rb b/spec/rggen/systemverilog/rtl/bit_field/type/rwhw_spec.rb new file mode 100644 index 0000000..3e98cdb --- /dev/null +++ b/spec/rggen/systemverilog/rtl/bit_field/type/rwhw_spec.rb @@ -0,0 +1,615 @@ +# frozen_string_literal: true + +RSpec.describe 'bit_field/type/rwhw' do + include_context 'clean-up builder' + include_context 'bit field rtl common' + + before(:all) do + RgGen.enable(:bit_field, :type, [:rw, :rwhw]) + end + + let(:bit_fields) do + create_bit_fields do + byte_size 256 + + register do + name 'register_0' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rwhw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rwhw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rwhw; initial_value 0; reference 'register_4.bit_field_0' } + end + + register do + name 'register_1' + size [4] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rwhw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rwhw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rwhw; initial_value 0; reference 'register_4.bit_field_0' } + end + + register do + name 'register_2' + size [2, 2] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rwhw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rwhw; initial_value 0; reference 'register_4.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rwhw; initial_value 0; reference 'register_4.bit_field_0' } + end + + register_file do + name 'register_file_3' + size [2, 2] + register_file do + name 'register_file_0' + register do + name 'register_0' + size [2, 2] + bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 1; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_1'; bit_assignment lsb: 1, width: 1; type :rwhw; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } + bit_field { name 'bit_field_2'; bit_assignment lsb: 4, width: 2; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_3'; bit_assignment lsb: 6, width: 2; type :rwhw; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } + bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4, sequence_size: 2, step: 8; type :rwhw; initial_value 0 } + bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4, sequence_size: 2, step: 8; type :rwhw; initial_value 0; reference 'register_file_5.register_file_0.register_0.bit_field_0' } + end + end + end + + register do + name 'register_4' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rw; initial_value 0 } + end + + register_file do + name 'register_file_5' + size [2, 2] + register_file do + name 'register_file_0' + register do + name 'register_0' + bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rw; initial_value 0 } + end + end + end + end + end + + it '入力ポート#value_in/出力ポート#value_outを持つ' do + expect(bit_fields[0]).to have_port( + :register_block, :value_in, + name: 'i_register_0_bit_field_0', direction: :input, data_type: :logic, width: 1 + ) + expect(bit_fields[0]).to have_port( + :register_block, :value_out, + name: 'o_register_0_bit_field_0', direction: :output, data_type: :logic, width: 1 + ) + + expect(bit_fields[2]).to have_port( + :register_block, :value_in, + name: 'i_register_0_bit_field_2', direction: :input, data_type: :logic, width: 2 + ) + expect(bit_fields[2]).to have_port( + :register_block, :value_out, + name: 'o_register_0_bit_field_2', direction: :output, data_type: :logic, width: 2 + ) + + expect(bit_fields[4]).to have_port( + :register_block, :value_in, + name: 'i_register_0_bit_field_4', direction: :input, data_type: :logic, width: 4, + array_size: [2], array_format: array_port_format + ) + expect(bit_fields[4]).to have_port( + :register_block, :value_out, + name: 'o_register_0_bit_field_4', direction: :output, data_type: :logic, width: 4, + array_size: [2], array_format: array_port_format + ) + + expect(bit_fields[6]).to have_port( + :register_block, :value_in, + name: 'i_register_1_bit_field_0', direction: :input, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[6]).to have_port( + :register_block, :value_out, + name: 'o_register_1_bit_field_0', direction: :output, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + + expect(bit_fields[8]).to have_port( + :register_block, :value_in, + name: 'i_register_1_bit_field_2', direction: :input, data_type: :logic, width: 2, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[8]).to have_port( + :register_block, :value_out, + name: 'o_register_1_bit_field_2', direction: :output, data_type: :logic, width: 2, + array_size: [4], array_format: array_port_format + ) + + expect(bit_fields[10]).to have_port( + :register_block, :value_in, + name: 'i_register_1_bit_field_4', direction: :input, data_type: :logic, width: 4, + array_size: [4, 2], array_format: array_port_format + ) + expect(bit_fields[10]).to have_port( + :register_block, :value_out, + name: 'o_register_1_bit_field_4', direction: :output, data_type: :logic, width: 4, + array_size: [4, 2], array_format: array_port_format + ) + + expect(bit_fields[12]).to have_port( + :register_block, :value_in, + name: 'i_register_2_bit_field_0', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[12]).to have_port( + :register_block, :value_out, + name: 'o_register_2_bit_field_0', direction: :output, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + + expect(bit_fields[14]).to have_port( + :register_block, :value_in, + name: 'i_register_2_bit_field_2', direction: :input, data_type: :logic, width: 2, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[14]).to have_port( + :register_block, :value_out, + name: 'o_register_2_bit_field_2', direction: :output, data_type: :logic, width: 2, + array_size: [2, 2], array_format: array_port_format + ) + + expect(bit_fields[16]).to have_port( + :register_block, :value_in, + name: 'i_register_2_bit_field_4', direction: :input, data_type: :logic, width: 4, + array_size: [2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[16]).to have_port( + :register_block, :value_out, + name: 'o_register_2_bit_field_4', direction: :output, data_type: :logic, width: 4, + array_size: [2, 2, 2], array_format: array_port_format + ) + + expect(bit_fields[18]).to have_port( + :register_block, :value_in, + name: 'i_register_file_3_register_file_0_register_0_bit_field_0', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[18]).to have_port( + :register_block, :value_out, + name: 'o_register_file_3_register_file_0_register_0_bit_field_0', direction: :output, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + + expect(bit_fields[20]).to have_port( + :register_block, :value_in, + name: 'i_register_file_3_register_file_0_register_0_bit_field_2', direction: :input, data_type: :logic, width: 2, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[20]).to have_port( + :register_block, :value_out, + name: 'o_register_file_3_register_file_0_register_0_bit_field_2', direction: :output, data_type: :logic, width: 2, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + + expect(bit_fields[22]).to have_port( + :register_block, :value_in, + name: 'i_register_file_3_register_file_0_register_0_bit_field_4', direction: :input, data_type: :logic, width: 4, + array_size: [2, 2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[22]).to have_port( + :register_block, :value_out, + name: 'o_register_file_3_register_file_0_register_0_bit_field_4', direction: :output, data_type: :logic, width: 4, + array_size: [2, 2, 2, 2, 2], array_format: array_port_format + ) + end + + context '参照ビットフィールドを持たない場合' do + it '入力ポート#validを持つ' do + expect(bit_fields[0]).to have_port( + :register_block, :valid, + name: 'i_register_0_bit_field_0_valid', direction: :input, data_type: :logic, width: 1 + ) + expect(bit_fields[2]).to have_port( + :register_block, :valid, + name: 'i_register_0_bit_field_2_valid', direction: :input, data_type: :logic, width: 1 + ) + expect(bit_fields[4]).to have_port( + :register_block, :valid, + name: 'i_register_0_bit_field_4_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2], array_format: array_port_format + ) + + expect(bit_fields[6]).to have_port( + :register_block, :valid, + name: 'i_register_1_bit_field_0_valid', direction: :input, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[8]).to have_port( + :register_block, :valid, + name: 'i_register_1_bit_field_2_valid', direction: :input, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[10]).to have_port( + :register_block, :valid, + name: 'i_register_1_bit_field_4_valid', direction: :input, data_type: :logic, width: 1, + array_size: [4, 2], array_format: array_port_format + ) + + expect(bit_fields[12]).to have_port( + :register_block, :valid, + name: 'i_register_2_bit_field_0_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[14]).to have_port( + :register_block, :valid, + name: 'i_register_2_bit_field_2_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[16]).to have_port( + :register_block, :valid, + name: 'i_register_2_bit_field_4_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2], array_format: array_port_format + ) + + expect(bit_fields[18]).to have_port( + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_0_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[20]).to have_port( + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_2_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[22]).to have_port( + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_4_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2, 2], array_format: array_port_format + ) + end + end + + context '参照ビットフィールドを持つ場合' do + it '入力ポート#validを持たない' do + expect(bit_fields[1]).to not_have_port( + :register_block, :valid, + name: 'i_register_0_bit_field_1_valid', direction: :input, data_type: :logic, width: 1 + ) + expect(bit_fields[3]).to not_have_port( + :register_block, :valid, + name: 'i_register_0_bit_field_3_valid', direction: :input, data_type: :logic, width: 1 + ) + expect(bit_fields[5]).to not_have_port( + :register_block, :valid, + name: 'i_register_0_bit_field_5_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2], array_format: array_port_format + ) + + expect(bit_fields[7]).to not_have_port( + :register_block, :valid, + name: 'i_register_1_bit_field_1_valid', direction: :input, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[9]).to not_have_port( + :register_block, :valid, + name: 'i_register_1_bit_field_3_valid', direction: :input, data_type: :logic, width: 1, + array_size: [4], array_format: array_port_format + ) + expect(bit_fields[11]).to not_have_port( + :register_block, :valid, + name: 'i_register_1_bit_field_5_valid', direction: :input, data_type: :logic, width: 1, + array_size: [4, 2], array_format: array_port_format + ) + + expect(bit_fields[13]).to not_have_port( + :register_block, :valid, + name: 'i_register_2_bit_field_1_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[15]).to not_have_port( + :register_block, :valid, + name: 'i_register_2_bit_field_3_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2], array_format: array_port_format + ) + expect(bit_fields[17]).to not_have_port( + :register_block, :valid, + name: 'i_register_2_bit_field_5_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2], array_format: array_port_format + ) + + expect(bit_fields[19]).to not_have_port( + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_1_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[21]).to not_have_port( + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_3_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2], array_format: array_port_format + ) + expect(bit_fields[23]).to not_have_port( + :register_block, :valid, + name: 'i_register_file_3_register_file_0_register_0_bit_field_5_valid', direction: :input, data_type: :logic, width: 1, + array_size: [2, 2, 2, 2, 2], array_format: array_port_format + ) + end + end + + describe '#generate_code' do + let(:array_port_format) { :packed } + + it 'rggen_bit_fieldをインスタンスするコードを出力する' do + expect(bit_fields[0]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (i_register_0_bit_field_0_valid), + .i_hw_write_data (i_register_0_bit_field_0), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_0), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[1]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (1), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (register_if[25].value[0+:1]), + .i_hw_write_data (i_register_0_bit_field_1), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_1), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[2]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (i_register_0_bit_field_2_valid), + .i_hw_write_data (i_register_0_bit_field_2), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_2), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[3]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (2), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (register_if[25].value[0+:1]), + .i_hw_write_data (i_register_0_bit_field_3), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_3), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[4]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (i_register_0_bit_field_4_valid[i]), + .i_hw_write_data (i_register_0_bit_field_4[i]), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_4[i]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[5]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (register_if[25].value[0+:1]), + .i_hw_write_data (i_register_0_bit_field_5[i]), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_0_bit_field_5[i]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[10]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (i_register_1_bit_field_4_valid[i][j]), + .i_hw_write_data (i_register_1_bit_field_4[i][j]), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_1_bit_field_4[i][j]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[11]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (register_if[25].value[0+:1]), + .i_hw_write_data (i_register_1_bit_field_5[i][j]), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_1_bit_field_5[i][j]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[16]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (i_register_2_bit_field_4_valid[i][j][k]), + .i_hw_write_data (i_register_2_bit_field_4[i][j][k]), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_2_bit_field_4[i][j][k]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[17]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (register_if[25].value[0+:1]), + .i_hw_write_data (i_register_2_bit_field_5[i][j][k]), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_2_bit_field_5[i][j][k]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[22]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (i_register_file_3_register_file_0_register_0_bit_field_4_valid[i][j][k][l][m]), + .i_hw_write_data (i_register_file_3_register_file_0_register_0_bit_field_4[i][j][k][l][m]), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_3_register_file_0_register_0_bit_field_4[i][j][k][l][m]), + .o_value_unmasked () + ); + CODE + + expect(bit_fields[23]).to generate_code(:bit_field, :top_down, <<~'CODE') + rggen_bit_field #( + .WIDTH (4), + .INITIAL_VALUE (INITIAL_VALUE) + ) u_bit_field ( + .i_clk (i_clk), + .i_rst_n (i_rst_n), + .bit_field_if (bit_field_sub_if), + .o_write_trigger (), + .o_read_trigger (), + .i_sw_write_enable ('1), + .i_hw_write_enable (register_if[26+2*i+j].value[0+:1]), + .i_hw_write_data (i_register_file_3_register_file_0_register_0_bit_field_5[i][j][k][l][m]), + .i_hw_set ('0), + .i_hw_clear ('0), + .i_value ('0), + .i_mask ('1), + .o_value (o_register_file_3_register_file_0_register_0_bit_field_5[i][j][k][l][m]), + .o_value_unmasked () + ); + CODE + end + end +end diff --git a/spec/rggen/systemverilog/rtl/bit_field/type/rws_spec.rb b/spec/rggen/systemverilog/rtl/bit_field/type/rws_spec.rb index a539b70..0cd17a9 100644 --- a/spec/rggen/systemverilog/rtl/bit_field/type/rws_spec.rb +++ b/spec/rggen/systemverilog/rtl/bit_field/type/rws_spec.rb @@ -1,3 +1,4 @@ + # frozen_string_literal: true RSpec.describe 'bit_field/type/rws' do @@ -81,129 +82,63 @@ end end - it '入力ポート#value_in/出力ポート#value_outを持つ' do - expect(bit_fields[0]).to have_port( - :register_block, :value_in, - name: 'i_register_0_bit_field_0', direction: :input, data_type: :logic, width: 1 - ) + it '出力ポート#value_outを持つ' do expect(bit_fields[0]).to have_port( :register_block, :value_out, name: 'o_register_0_bit_field_0', direction: :output, data_type: :logic, width: 1 ) - - expect(bit_fields[2]).to have_port( - :register_block, :value_in, - name: 'i_register_0_bit_field_2', direction: :input, data_type: :logic, width: 2 - ) expect(bit_fields[2]).to have_port( :register_block, :value_out, name: 'o_register_0_bit_field_2', direction: :output, data_type: :logic, width: 2 ) - - expect(bit_fields[4]).to have_port( - :register_block, :value_in, - name: 'i_register_0_bit_field_4', direction: :input, data_type: :logic, width: 4, - array_size: [2], array_format: array_port_format - ) expect(bit_fields[4]).to have_port( :register_block, :value_out, name: 'o_register_0_bit_field_4', direction: :output, data_type: :logic, width: 4, array_size: [2], array_format: array_port_format ) - expect(bit_fields[6]).to have_port( - :register_block, :value_in, - name: 'i_register_1_bit_field_0', direction: :input, data_type: :logic, width: 1, - array_size: [4], array_format: array_port_format - ) expect(bit_fields[6]).to have_port( :register_block, :value_out, name: 'o_register_1_bit_field_0', direction: :output, data_type: :logic, width: 1, array_size: [4], array_format: array_port_format ) - - expect(bit_fields[8]).to have_port( - :register_block, :value_in, - name: 'i_register_1_bit_field_2', direction: :input, data_type: :logic, width: 2, - array_size: [4], array_format: array_port_format - ) expect(bit_fields[8]).to have_port( :register_block, :value_out, name: 'o_register_1_bit_field_2', direction: :output, data_type: :logic, width: 2, array_size: [4], array_format: array_port_format ) - - expect(bit_fields[10]).to have_port( - :register_block, :value_in, - name: 'i_register_1_bit_field_4', direction: :input, data_type: :logic, width: 4, - array_size: [4, 2], array_format: array_port_format - ) expect(bit_fields[10]).to have_port( :register_block, :value_out, name: 'o_register_1_bit_field_4', direction: :output, data_type: :logic, width: 4, array_size: [4, 2], array_format: array_port_format ) - expect(bit_fields[12]).to have_port( - :register_block, :value_in, - name: 'i_register_2_bit_field_0', direction: :input, data_type: :logic, width: 1, - array_size: [2, 2], array_format: array_port_format - ) expect(bit_fields[12]).to have_port( :register_block, :value_out, name: 'o_register_2_bit_field_0', direction: :output, data_type: :logic, width: 1, array_size: [2, 2], array_format: array_port_format ) - - expect(bit_fields[14]).to have_port( - :register_block, :value_in, - name: 'i_register_2_bit_field_2', direction: :input, data_type: :logic, width: 2, - array_size: [2, 2], array_format: array_port_format - ) expect(bit_fields[14]).to have_port( :register_block, :value_out, name: 'o_register_2_bit_field_2', direction: :output, data_type: :logic, width: 2, array_size: [2, 2], array_format: array_port_format ) - - expect(bit_fields[16]).to have_port( - :register_block, :value_in, - name: 'i_register_2_bit_field_4', direction: :input, data_type: :logic, width: 4, - array_size: [2, 2, 2], array_format: array_port_format - ) expect(bit_fields[16]).to have_port( :register_block, :value_out, name: 'o_register_2_bit_field_4', direction: :output, data_type: :logic, width: 4, array_size: [2, 2, 2], array_format: array_port_format ) - expect(bit_fields[18]).to have_port( - :register_block, :value_in, - name: 'i_register_file_3_register_file_0_register_0_bit_field_0', direction: :input, data_type: :logic, width: 1, - array_size: [2, 2, 2, 2], array_format: array_port_format - ) expect(bit_fields[18]).to have_port( :register_block, :value_out, name: 'o_register_file_3_register_file_0_register_0_bit_field_0', direction: :output, data_type: :logic, width: 1, array_size: [2, 2, 2, 2], array_format: array_port_format ) - - expect(bit_fields[20]).to have_port( - :register_block, :value_in, - name: 'i_register_file_3_register_file_0_register_0_bit_field_2', direction: :input, data_type: :logic, width: 2, - array_size: [2, 2, 2, 2], array_format: array_port_format - ) expect(bit_fields[20]).to have_port( :register_block, :value_out, name: 'o_register_file_3_register_file_0_register_0_bit_field_2', direction: :output, data_type: :logic, width: 2, array_size: [2, 2, 2, 2], array_format: array_port_format ) - - expect(bit_fields[22]).to have_port( - :register_block, :value_in, - name: 'i_register_file_3_register_file_0_register_0_bit_field_4', direction: :input, data_type: :logic, width: 4, - array_size: [2, 2, 2, 2, 2], array_format: array_port_format - ) expect(bit_fields[22]).to have_port( :register_block, :value_out, name: 'o_register_file_3_register_file_0_register_0_bit_field_4', direction: :output, data_type: :logic, width: 4, @@ -350,7 +285,8 @@ expect(bit_fields[0]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (1), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -358,9 +294,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_0_bit_field_0_set), - .i_hw_write_data (i_register_0_bit_field_0), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_0_bit_field_0_set), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -372,7 +308,8 @@ expect(bit_fields[1]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (1), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -380,9 +317,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (register_if[25].value[0+:1]), - .i_hw_write_data (i_register_0_bit_field_1), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -394,7 +331,8 @@ expect(bit_fields[2]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (2), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -402,9 +340,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_0_bit_field_2_set), - .i_hw_write_data (i_register_0_bit_field_2), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_0_bit_field_2_set), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -416,7 +354,8 @@ expect(bit_fields[3]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (2), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -424,9 +363,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (register_if[25].value[0+:1]), - .i_hw_write_data (i_register_0_bit_field_3), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -438,7 +377,8 @@ expect(bit_fields[4]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (4), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -446,9 +386,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_0_bit_field_4_set[i]), - .i_hw_write_data (i_register_0_bit_field_4[i]), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_0_bit_field_4_set[i]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -460,7 +400,8 @@ expect(bit_fields[5]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (4), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -468,9 +409,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (register_if[25].value[0+:1]), - .i_hw_write_data (i_register_0_bit_field_5[i]), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -482,7 +423,8 @@ expect(bit_fields[10]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (4), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -490,9 +432,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_1_bit_field_4_set[i][j]), - .i_hw_write_data (i_register_1_bit_field_4[i][j]), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_1_bit_field_4_set[i][j]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -504,7 +446,8 @@ expect(bit_fields[11]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (4), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -512,9 +455,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (register_if[25].value[0+:1]), - .i_hw_write_data (i_register_1_bit_field_5[i][j]), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -526,7 +469,8 @@ expect(bit_fields[16]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (4), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -534,9 +478,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_2_bit_field_4_set[i][j][k]), - .i_hw_write_data (i_register_2_bit_field_4[i][j][k]), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_2_bit_field_4_set[i][j][k]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -548,7 +492,8 @@ expect(bit_fields[17]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (4), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -556,9 +501,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (register_if[25].value[0+:1]), - .i_hw_write_data (i_register_2_bit_field_5[i][j][k]), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[25].value[0+:1]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -570,7 +515,8 @@ expect(bit_fields[22]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (4), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -578,9 +524,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (i_register_file_3_register_file_0_register_0_bit_field_4_set[i][j][k][l][m]), - .i_hw_write_data (i_register_file_3_register_file_0_register_0_bit_field_4[i][j][k][l][m]), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (i_register_file_3_register_file_0_register_0_bit_field_4_set[i][j][k][l][m]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1), @@ -592,7 +538,8 @@ expect(bit_fields[23]).to generate_code(:bit_field, :top_down, <<~'CODE') rggen_bit_field #( .WIDTH (4), - .INITIAL_VALUE (INITIAL_VALUE) + .INITIAL_VALUE (INITIAL_VALUE), + .HW_SET_WIDTH (1) ) u_bit_field ( .i_clk (i_clk), .i_rst_n (i_rst_n), @@ -600,9 +547,9 @@ .o_write_trigger (), .o_read_trigger (), .i_sw_write_enable ('1), - .i_hw_write_enable (register_if[26+2*i+j].value[0+:1]), - .i_hw_write_data (i_register_file_3_register_file_0_register_0_bit_field_5[i][j][k][l][m]), - .i_hw_set ('0), + .i_hw_write_enable ('0), + .i_hw_write_data ('0), + .i_hw_set (register_if[26+2*i+j].value[0+:1]), .i_hw_clear ('0), .i_value ('0), .i_mask ('1),