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core
docs
dv
riscv-tools @ 4635ab6
rtl
sw
synth
.gitignore
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README.md

README.md

tcnj_ic2

Front-End Design for RISC-V Microcontroller Application-Specific Integrated Circuit (ASIC)

Vivado instructions: https://github.com/richlvnsn/tcnj_ic2/wiki/Vivado-Instructions

core

Verilog files for the vscale RISC-V core implementation.

docs

Reference materials.

dv

Design verification files.

rtl

Register transfer level Verilog files for all modules other than the core.

sw

Software.

synth

Design constraints and TCL files required for synthesis, implementation, and bitstream generation.

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