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Verilog Code and test bench of the module

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README.md

Introduction

This repository contains verilog code for a serial 3 bit sequence detector. This repository is made to test if I can use git with verilog code written in xilinx ISE webpack.


About Verilog Module

Input Ouput Specifications


Inputs

  • si - Serial Input
  • clk - Clock

Output

  • detected - Shows if the sequence is detected or not

Registers

  • CurrentSequence - Holds the current sequence of 3 bits to be compared with the sequence to be detected.

Description

The circuit takes in one bit at each positive edge of the clock. The bit is added to the lsb of the internal register CurrentSequence. The CurrentSequence is then compared with the sequence to be detected, if found same detected is made high.The sequence to be dected is parameterized in the code as Sequence.

About Test Bench

Parameters

  • NoOfTestingBits - Gives number of bits used for testing
  • seed - Seed used for $random system task.

The test bench generates a bitstream of fixed length given by NoOfTestingBits parameter. Each bit is randomly generated using the $random(seed) system call where seed is parameter.

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