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checkpoint commit: compiles

structural cluster cache FIFOs hooked up, clocked
requests handled at dummy memside routine (emulated)
passes most tests, but may not complete long RTM (dmm, cg)
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1 parent 3913847 commit eac7a3320d472057324489f5ea708b7871c01167 @drjohnson drjohnson committed Mar 26, 2012
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2 rigel-sim/include/cluster/cluster_cache_base.h
@@ -54,6 +54,8 @@ class ClusterCacheBase : public ComponentBase {
protected:
+ int numcores;
+
std::vector< InPortBase<Packet*>* > coreside_ins;
std::vector< OutPortBase<Packet*>* > coreside_outs;
View
28 rigel-sim/include/cluster/cluster_cache_structural.h
@@ -35,30 +35,32 @@ class ClusterCacheStructural : public ClusterCacheBase {
void Dump();
void Heartbeat();
-
- /// REMOVE ME: FIXME TODO HACK -- replace this with proper generic
- //connections
-// InPortBase<Packet*>* getCoreSideInPort(int p) { return coreside_ins[p]; }
-// OutPortBase<Packet*>* getCoreSideOutPort(int p) { return coreside_outs[p]; }
-
protected:
std::vector<clustercache::LDLSTC_entry_t> LinkTable;
-// std::vector< InPortBase<Packet*>* > coreside_ins;
-// std::vector< OutPortBase<Packet*>* > coreside_outs;
-
private: // we don't want these visible to inherited classes
void doMemoryAccess(Packet* p);
void doLocalAtomic(Packet* p);
void doGlobalAtomic(Packet* p);
-
- port_status_t FunctionalMemoryRequest(Packet* p);
- fifo< std::pair<uint64_t,Packet*> > outpackets;
+ void handleCoreSideInputs();
+ void handleCoreSideRequests();
+ void handleCoreSideReplies();
+ void handleCCacheRequests();
+ void handleCCacheReplies();
+ void memsideBypass();
+ void handleMemorySideReplies();
+
+ std::vector< fifo<Packet*> > coreside_requests;
+ std::vector< fifo<Packet*> > coreside_replies;
+
+ fifo<Packet*> ccache_requests;
+ fifo<Packet*> ccache_replies;
- int fixed_latency;
+ fifo<Packet*> memside_requests;
+ fifo<Packet*> memside_replies;
};
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1 rigel-sim/include/core/core_functional.h
@@ -31,7 +31,6 @@ class CoreFunctional : public CoreBase {
public:
/// constructor
CoreFunctional(rigel::ConstructionPayload cp);
- //ClusterCacheFunctional* ccache);
/// destructor
~CoreFunctional();
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37 rigel-sim/include/packet/packet.h
@@ -3,6 +3,8 @@
#include "define.h"
+// memory request packet
+
class Packet {
public:
@@ -11,14 +13,17 @@ class Packet {
Packet(icmsg_type_t m,
uint32_t a,
uint32_t d,
+ uint32_t pc,
int gcoreid,
int gtid
) :
_msgType(m),
_addr(a),
_data(d),
+ _pc(pc),
_gcoreid(gcoreid),
_gtid(gtid),
+ _birthday(rigel::CURR_CYCLE),
_completed(false)
{ };
@@ -27,8 +32,11 @@ class Packet {
_msgType(m),
_addr(0),
_data(0),
+ _pc(0),
_gcoreid(-1), // invalid
- _gtid(-1) // invalid
+ _gtid(-1), // invalid
+ _birthday(rigel::CURR_CYCLE),
+ _completed(false)
{
};
@@ -44,8 +52,8 @@ class Packet {
/// Dump
void Dump() {
- printf("m: %d a:0x%08x d:0x%08x c:%d gtid:%d\n",
- _msgType, _addr, _data, _gcoreid, _gtid);
+ printf("m: %d a:0x%08x d:0x%08x pc:0x%08x c:%d gtid:%d\n",
+ _msgType, _addr, _data, _pc, _gcoreid, _gtid);
};
/// accessors
@@ -63,21 +71,34 @@ class Packet {
void addr(uint32_t a) { _addr = a; }
void data(uint32_t d) { _data = d; }
+ void pc(uint32_t p) { _pc = p; }
void msgType(icmsg_type_t t) { _msgType = t; }
void gAtomicOperand( uint32_t o ) { _gatomic_operand = o; }
+ // TODO: these features could be shared with instr packets in a base class
+ // along with counting dynamic (live) and total instances
+ uint64_t birthday() { return _birthday; }
+ uint64_t age() { return rigel::CURR_CYCLE - _birthday; }
+
bool isCompleted() { return _completed; }
void setCompleted() { _completed = true; }
private:
- icmsg_type_t _msgType; // interconnect message type
- uint32_t _addr;
- uint32_t _data;
- int _gcoreid; /// global core ID (should REMOVE, use TID)
- int _gtid; /// global thread ID
+ icmsg_type_t _msgType; ///< interconnect message type
+ uint32_t _addr; ///< address of this request
+ uint32_t _data; ///<
+
+ uint32_t _pc; ///< pc of instruction that generated request, if relevant
+
+ int _gcoreid; ///< global core ID (should REMOVE, use TID)
+ int _gtid; ///< global thread ID
uint32_t _gatomic_operand; /// global atomic operand
+ uint64_t _birthday; ///< cycle this was constructed
+
+ uint64_t _id; ///< unique (modulo 2^64) identifier assigned at creation
+
bool _completed; /// has been fully serviced
};
View
2 rigel-sim/include/port/port.h
@@ -165,8 +165,8 @@ class OutPortBase : public PortBase {
friend class PortManager<T>;
private:
- InPortBase<T>* _connection;
std::string _name; ///< port name
+ InPortBase<T>* _connection;
};
View
3 rigel-sim/include/sim.h
@@ -19,7 +19,8 @@
#define DPRINTOLD(...) fprintf ( stdout, __VA_ARGS__ )
#define DPRINT(cond,...) { if (cond) {fprintf ( stdout, __VA_ARGS__ );} }
//#define DRIGEL(blah) blah
-#define DRIGEL(blah)
+#define DRIGEL(p,blah)
+//#define DRIGEL(p,blah) if(p) {blah;}
//#define DPRINT
// XXX: user.config must be hand made for each user. Check user.config.example
View
4 rigel-sim/include/util/fifo.h
@@ -38,6 +38,10 @@ class fifo : public std::queue<T> {
}
+ void Dump() {
+
+ }
+
private:
const unsigned _capacity;
View
5 rigel-sim/src/cluster/cluster_cache_base.cpp
@@ -9,8 +9,9 @@ ClusterCacheBase::ClusterCacheBase(rigel::ConstructionPayload cp)
: ComponentBase(cp.parent,
cp.change_name("ClusterCacheBase").component_name.c_str(),
*(cp.change_component_count(ClusterCacheBaseCount).component_count)),
- coreside_ins(rigel::CORES_PER_CLUSTER), // FIXME: make this non-const
- coreside_outs(rigel::CORES_PER_CLUSTER), // FIXME: make this non-const
+ numcores(rigel::CORES_PER_CLUSTER), // FIXME: make this non-const
+ coreside_ins(numcores),
+ coreside_outs(numcores),
mem_backing_store(cp.backing_store)
{
}
View
3 rigel-sim/src/cluster/cluster_cache_functional.cpp
@@ -11,7 +11,7 @@
#define DB_CC 0
-#define CF_FIXED_LATENCY 20
+#define CF_FIXED_LATENCY 0
/// constructor
ClusterCacheFunctional::ClusterCacheFunctional(
@@ -235,6 +235,7 @@ ClusterCacheFunctional::doLocalAtomic(PacketPtr p) {
}
break;
default:
+ p->Dump();
throw ExitSim("invalid message type in packet!");
}
p->setCompleted(); // access handled, return to core
View
193 rigel-sim/src/cluster/cluster_cache_structural.cpp
@@ -11,8 +11,6 @@
#define DB_CC 0
-#define CF_FIXED_LATENCY 2
-
/// constructor
ClusterCacheStructural::ClusterCacheStructural(
rigel::ConstructionPayload cp,
@@ -21,28 +19,23 @@ ClusterCacheStructural::ClusterCacheStructural(
) :
ClusterCacheBase(cp.change_name("ClusterCacheStructural")),
LinkTable(rigel::THREADS_PER_CLUSTER), // TODO FIXME dynamic
-// coreside_ins(rigel::CORES_PER_CLUSTER), // FIXME: make this non-const
-// coreside_outs(rigel::CORES_PER_CLUSTER), // FIXME: make this non-const
- outpackets(1),
- fixed_latency(CF_FIXED_LATENCY)
+ // FIXME: resize these later
+ coreside_requests(numcores, fifo<Packet*>(rigel::THREADS_PER_CLUSTER)),
+ coreside_replies(numcores, fifo<Packet*>(rigel::THREADS_PER_CLUSTER)),
+ ccache_requests(99),
+ ccache_replies(99),
+ memside_requests(99),
+ memside_replies(99)
{
- // TODO: make this an internal class of the port, so we don't have to specify port_status_t ?
- CallbackWrapper<Packet*,port_status_t>* mcb
- = new MemberCallbackWrapper<
- ClusterCacheStructural,
- Packet*,
- port_status_t,
- &ClusterCacheStructural::FunctionalMemoryRequest>(this);
-
- for (int i = 0; i < coreside_ins.size(); i++) {
- std::string n = PortName( name(), id(), "coreside_in", i );
- coreside_ins[i] = new InPortCallback<Packet*>(n, mcb);
+ for (unsigned i = 0; i < coreside_ins.size(); i++) {
+ std::string pname = PortName( name(), id(), "coreside_in", i );
+ coreside_ins[i] = new InPortBase<Packet*>(pname);
}
- for (int i = 0; i < coreside_outs.size(); i++) {
- std::string n = PortName( name(), id(), "coreside_out", i );
- coreside_outs[i] = new OutPortBase<Packet*>(n);
+ for (unsigned i = 0; i < coreside_outs.size(); i++) {
+ std::string pname = PortName( name(), id(), "coreside_out", i );
+ coreside_outs[i] = new OutPortBase<Packet*>(pname);
}
}
@@ -52,55 +45,144 @@ ClusterCacheStructural::ClusterCacheStructural(
int
ClusterCacheStructural::PerCycle() {
- if (!outpackets.empty()) {
- if (outpackets.front().first <= rigel::CURR_CYCLE) {
- Packet* p;
- p = outpackets.front().second;
+ //
+ handleCoreSideReplies();
- doMemoryAccess(p);
- assert(p!=0);
+ //
+ handleCCacheReplies();
+
+ // should consume memory-side inports...
+ handleMemorySideReplies();
- coreside_outs[p->local_coreid()]->sendMsg(p);
- outpackets.pop();
- }
- }
+ // handleMemsideRequests?
+ memsideBypass();
+
+ //
+ handleCCacheRequests();
+
+ //
+ handleCoreSideRequests();
+
+ // consume core-side inports
+ handleCoreSideInputs();
return 0;
+
};
+
+/// handleCoreSideInputs
+///
+/// check each core's port
+/// if the L1 hits, then
void
-ClusterCacheStructural::EndSim() {
+ClusterCacheStructural::handleCoreSideInputs() {
+ DPRINT(DB_CC,"%s\n",__func__);
+
+ for (int i = 0; i < numcores; i++) {
+ Packet* p;
+ if (p = coreside_ins[i]->read()) {
+ DRIGEL(DB_CC,p->Dump();)
+ if (false) { //CheckL1(i, p)) { // HIT!
+ // put in the L1 response queue
+ coreside_replies[i].push(p);
+ } else { // Miss
+ // put in the core's L1 miss queue
+ coreside_requests[i].push(p);
+ }
+ }
+ }
-};
+}
void
-ClusterCacheStructural::Dump() {
-
-};
+ClusterCacheStructural::handleCoreSideRequests() {
+ DPRINT(DB_CC,"%s\n",__func__);
+
+ for (unsigned i = 0; i < coreside_requests.size(); i++) {
+ if (!coreside_requests[i].empty()) {
+ Packet* p = coreside_requests[i].front();
+ DRIGEL(DB_CC,p->Dump();)
+ ccache_requests.push(p);
+ coreside_requests[i].pop();
+ }
+ }
+
+}
void
-ClusterCacheStructural::Heartbeat() {};
+ClusterCacheStructural::handleCCacheRequests() {
+ DPRINT(DB_CC,"%s\n",__func__);
+
+ while (!ccache_requests.empty()) {
+ Packet* p = ccache_requests.front();
+ DRIGEL(DB_CC,p->Dump();)
+ memside_requests.push(p);
+ ccache_requests.pop();
+ }
+}
-/// CCFunctional specific
-port_status_t
-ClusterCacheStructural::FunctionalMemoryRequest(Packet* p) {
+void
+ClusterCacheStructural::handleMemorySideReplies() {
+ DPRINT(DB_CC,"%s\n",__func__);
+
+ while (!memside_replies.empty()) {
+ Packet* p = memside_replies.front();
+ DRIGEL(DB_CC,p->Dump();)
+ ccache_replies.push(p);
+ memside_replies.pop();
+ }
+
+}
- if (fixed_latency == 0) { // send immediately
+void
+ClusterCacheStructural::handleCCacheReplies() {
+ DPRINT(DB_CC,"%s\n",__func__);
+
+ while (!ccache_replies.empty()) {
+ Packet* p = ccache_replies.front();
+ DRIGEL(DB_CC,p->Dump();)
+ int map = p->local_coreid();
+ coreside_replies[map].push(p);
+ ccache_replies.pop();
+ }
+
+}
+
+void
+ClusterCacheStructural::memsideBypass() {
+ DPRINT(DB_CC,"%s\n",__func__);
+
+ while (!memside_requests.empty()) {
+ Packet* p = memside_requests.front();
+ DRIGEL(DB_CC,p->Dump();)
doMemoryAccess(p);
- assert(p!=0);
- coreside_outs[p->local_coreid()]->sendMsg(p);
- return ACK;
- } else {
- if ( outpackets.push( std::make_pair(rigel::CURR_CYCLE + fixed_latency, p) ) ) {
- return ACK;
- } else {
- return NACK;
- throw ExitSim("unhandled fifo overrun!");
+ memside_replies.push(p);
+ memside_requests.pop();
+ }
+
+}
+
+void
+ClusterCacheStructural::handleCoreSideReplies() {
+ DPRINT(DB_CC,"%s\n",__func__);
+
+ for (int i = 0; i < numcores; i++) {
+ if (!coreside_replies[i].empty()) {
+ Packet* p = coreside_replies[i].front();
+ DRIGEL(DB_CC,p->Dump();)
+ if (coreside_outs[i]->sendMsg(p) == ACK) {
+ coreside_replies[i].pop();
+ } else {
+ printf("%s: sendMsg() failed on port %d\n", __func__, i);
+ }
}
}
+
}
+
void
ClusterCacheStructural::doMemoryAccess(PacketPtr p) {
@@ -238,3 +320,16 @@ ClusterCacheStructural::doLocalAtomic(PacketPtr p) {
p->setCompleted(); // access handled, return to core
return;
};
+
+void
+ClusterCacheStructural::EndSim() {
+
+};
+
+void
+ClusterCacheStructural::Dump() {
+
+};
+
+void
+ClusterCacheStructural::Heartbeat() {};
View
9 rigel-sim/src/core/core_functional.cpp
@@ -39,13 +39,11 @@
///////////////////////////////////////////////////////////////////////////////
CoreFunctional::CoreFunctional(
rigel::ConstructionPayload cp
- //ClusterCacheFunctional *ccache
) :
CoreBase(cp.change_name("CoreFunctional")),
width(CF_WIDTH),
numthreads(rigel::THREADS_PER_CORE),
current_tid(0),
- //ccache(ccache),
syscall_handler(cp.syscall),
thread_state(numthreads)
{
@@ -414,6 +412,7 @@ CoreFunctional::doMem(PipePacket* instr) {
// new packet based on instr type
Packet* p = new Packet( rigel::instr_to_icmsg_full(instr->type()) );
+ p->pc(instr->pc());
if (instr->isAtomic()) {
DPRINT(DB_CF,"%s: isMem isAtomic\n", __func__);
@@ -500,15 +499,15 @@ CoreFunctional::doMem(PipePacket* instr) {
case I_LINE_FLUSH:
// do nothing for these in functional mode, for now, with no caches
instr->setCompleted();
- DRIGEL( printf("ignoring CACHECONTROL instruction for now...NOP\n"); )
+ DRIGEL(false,printf("ignoring CACHECONTROL instruction for now...NOP\n"); )
return; // since we don't actually sent this request
break;
default:
throw ExitSim("unhandled CacheControl operation?");
}
} else if (instr->isPrefetch()) {
instr->setCompleted();
- DRIGEL( printf("ignoring PREFETCH instruction for now...NOP\n"); )
+ DRIGEL(false,printf("ignoring PREFETCH instruction for now...NOP\n"); )
return; // since we don't actually sent this request
} else {
instr->Dump();
@@ -610,7 +609,7 @@ CoreFunctional::doSimSpecial(PipePacket* instr) {
rigel::RigelSYSCALL(addr,syscall_handler,mem_backing_store); break;
}
case I_EVENT:
- DRIGEL( printf("ignore I_EVENT event instruction for now...NOP\n"); )
+ DRIGEL(false,printf("ignore I_EVENT event instruction for now...NOP\n"); )
break;
case I_NOP:
break;
View
4 rigel-sim/src/isa/rigel_isa.cpp
@@ -330,13 +330,13 @@ RigelISA::execAddressGen(PipePacket* instr) {
case I_LINE_INV:
case I_LINE_FLUSH:
// do nothing for these in functional mode, for now, with no caches
- DRIGEL( printf("ignoring CACHECONTROL instruction for now...NOP\n"); )
+ DRIGEL(false, printf("ignoring CACHECONTROL instruction for now...NOP\n"); )
break;
default:
throw ExitSim("unhandled CacheControl operation?");
}
} else if (instr->isPrefetch()) {
- DRIGEL( printf("ignoring PREFETCH instruction for now...NOP\n"); )
+ DRIGEL(false, printf("ignoring PREFETCH instruction for now...NOP\n"); )
} else {
instr->Dump();
throw ExitSim("unknown memory operation!");

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