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Commits on Apr 11, 2012
  1. @mrj10
Commits on Apr 10, 2012
  1. @mrj10
  2. @drjohnson

    Merge branch 'dev' of /afs/crhc.illinois.edu/project/rigel/common/git…

    drjohnson committed
    …hub/rigelproject-release/rigel-sim into dev
  3. @mrj10

    Replace map with unordered_map to store precoded static instr info.

    mrj10 committed
    maps are backed by rbtrees and are slower than hashtable-backed maps
    when there are no ordering requirements.  this patch speeds up
    most simulations by 15-30%.
    
    right now, i statically resize the hash table to have as many buckets
    as static instructions in the binary; this heuristic may need to be
    tuned, or we may want to do without it altogether to prevent coupling
    between the ELF loader and PipePacket stuff.
Commits on Apr 9, 2012
  1. @drjohnson

    print out port, component connections in graphviz-friendly style

    drjohnson committed
    ports get ComponentBase* owners
    (incomplete, and the graphs are too huge at the moment)
Commits on Mar 29, 2012
  1. Silence a few compile warnings

    Matt Johnson committed
  2. Make a port.cpp, put the static PortName function there to silence co…

    Matt Johnson committed
    …mpile warnings
  3. Rename instrbase files to instr_base

    Matt Johnson committed
  4. Rename corebase files to core_base

    Matt Johnson committed
  5. Rename tilebase files to tile_base

    Matt Johnson committed
  6. Rename clusterbase files to cluster_base

    Matt Johnson committed
  7. Rename componentbase.h to component_base.h

    Matt Johnson committed
  8. Rename a few memory-related files, make MemoryTiming* Components.

    Matt Johnson committed
    Also made the RigelSim object a Component, because *it* should be
    the root of the component hierarchy, not the Chip, because the
    MemoryTiming object is a peer to Chip, not a subordinate or parent.
    
    In time, this assumption may change and MemoryTiming may become
    a child of Chip, but whatever object contains the backing store
    will still need to be a peer to Chip and a child of RigelSim.
    
    MemoryTiming* don't implement most of the ComponentBase() methods
    yet, but they can at least be clocked, heartbeated, etc. within
    the common framework.
Commits on Mar 28, 2012
  1. Remove rapidjson .svn

    Matt Johnson committed
Commits on Mar 27, 2012
  1. @drjohnson
Commits on Mar 26, 2012
  1. @drjohnson
  2. @drjohnson

    checkpoint commit: compiles

    drjohnson committed
    structural cluster cache FIFOs hooked up, clocked
    requests handled at dummy memside routine (emulated)
    passes most tests, but may not complete long RTM (dmm, cg)
Commits on Mar 25, 2012
  1. @drjohnson

    Large commit: forked cluster, cluster cache for non-functional modes

    drjohnson committed
    ClusterCacheBase has common functionality of CCacheFunctional,Structural
    various small updates and fixes
    Callback wrappers can specify a (templated) return type
    InPortCallback returns result of the callback, not always Ack
  2. @drjohnson

    cg test pipe diff out to file

    drjohnson committed
  3. @drjohnson
Commits on Mar 23, 2012
  1. @drjohnson
  2. @drjohnson
Commits on Mar 22, 2012
  1. @drjohnson

    tilenew cleanup

    drjohnson committed
  2. @drjohnson

    fork chip: ChipLegacy for old stuff, ChipTiled for new stuff

    drjohnson committed
    (user.config updates for this)
  3. @drjohnson
  4. @drjohnson

    minor bugfixes, naming

    drjohnson committed
  5. @drjohnson
  6. @drjohnson

    checkpoint commit: add tree network

    drjohnson committed
    segfaults
  7. @drjohnson
  8. @drjohnson
Commits on Mar 21, 2012
  1. @drjohnson

    checkpoint commit

    drjohnson committed
    rename ClusterSimple ClusterFunctional
    port name changes
    initial portmanager header (incomplete)
Commits on Mar 20, 2012
  1. @drjohnson

    cache code readability cleanup

    drjohnson committed
  2. @drjohnson
  3. @drjohnson

    stallable memory requests via ports for CF

    drjohnson committed
    multithreaded mode in CoreFunctional stalls and serializes threads on multicycle memory requests
    (who cares about perf, this mode is not for accurate perf modelling)
    commit missing rigel_isa file (functional instruction execution)
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