Permalink
Browse files

Cleared whitespaces in mpd files

  • Loading branch information...
rihuber committed Mar 27, 2012
1 parent 18ddf0b commit e2505cbdbca7fa01fbc9aa8a6aca6e2b550b71f5
@@ -20,25 +20,25 @@ BUS_INTERFACE BUS=upstream1, BUS_STD=noc_switch_upstream, BUS_TYPE=INITIATOR
PARAMETER gobalAddr=0, ASSIGNMENT=REQUIRE, DESC="The global address of the switch (must be unique in the design)", DT=integer, PERMIT=BASE_USER, RANGE=(0:31), TYPE=HDL
## Ports
-PORT reset = reset, DIR = I, SIGIS = RST
-
-PORT downstream0ReadEnable = downstream0ReadEnable, DIR = I, BUS = downstream0
-PORT downstream0Empty = downstream0Empty, DIR = O, BUS = downstream0
-PORT downstream0Data = downstream0Data, DIR = O, BUS = downstream0, VEC=[0:8]
-PORT downstream0ReadClockdownstream0ReadClock, SIGIS=Clk, DIR = I, BUS = downstream0
-
-PORT downstream1ReadEnable = downstream1ReadEnable, DIR = I, BUS = downstream1
-PORT downstream1Empty = downstream1Empty, DIR = O, BUS = downstream1
-PORT downstream1Data = downstream1Data, DIR = O, BUS = downstream1, VEC=[0:8]
-PORT downstream1ReadClockdownstream1ReadClock, SIGIS=Clk, DIR = I, BUS = downstream1
-
-PORT upstream0WriteEnable = upstream0WriteEnable, DIR = I, BUS = upstream0
-PORT upstream0Data = upstream0Data, DIR = I, BUS = upstream0, VEC=[0:8]
-PORT upstream0Full = upstream0Full, DIR = O, BUS = upstream0
-PORT upstream0WriteClockupstream0WriteClock, SIGIS=Clk, DIR = I, BUS = upstream0
-
-PORT upstream1WriteEnable = upstream1WriteEnable, DIR = I, BUS = upstream1
-PORT upstream1Data = upstream1Data, DIR = I, BUS = upstream1, VEC=[0:8]
-PORT upstream1Full = upstream1Full, DIR = O, BUS = upstream1
-PORT upstream1WriteClockupstream1WriteClock, SIGIS=Clk, DIR = I, BUS = upstream1
+PORT reset=reset, DIR=I, SIGIS=RST
+
+PORT downstream0ReadEnable=downstream0ReadEnable, DIR=I, BUS=downstream0
+PORT downstream0Empty=downstream0Empty, DIR=O, BUS=downstream0
+PORT downstream0Data=downstream0Data, DIR=O, BUS=downstream0, VEC=[0:8]
+PORT downstream0ReadClock=downstream0ReadClock, SIGIS=Clk, DIR=I, BUS=downstream0
+
+PORT downstream1ReadEnable=downstream1ReadEnable, DIR=I, BUS=downstream1
+PORT downstream1Empty=downstream1Empty, DIR=O, BUS=downstream1
+PORT downstream1Data=downstream1Data, DIR=O, BUS=downstream1, VEC=[0:8]
+PORT downstream1ReadClock=downstream1ReadClock, SIGIS=Clk, DIR=I, BUS=downstream1
+
+PORT upstream0WriteEnable=upstream0WriteEnable, DIR=I, BUS=upstream0
+PORT upstream0Data=upstream0Data, DIR=I, BUS=upstream0, VEC=[0:8]
+PORT upstream0Full=upstream0Full, DIR=O, BUS=upstream0
+PORT upstream0WriteClock=upstream0WriteClock, SIGIS=Clk, DIR=I, BUS=upstream0
+
+PORT upstream1WriteEnable=upstream1WriteEnable, DIR=I, BUS=upstream1
+PORT upstream1Data=upstream1Data, DIR=I, BUS=upstream1, VEC=[0:8]
+PORT upstream1Full=upstream1Full, DIR=O, BUS=upstream1
+PORT upstream1WriteClock=upstream1WriteClock, SIGIS=Clk, DIR=I, BUS=upstream1
END
@@ -45,15 +45,15 @@ PORT FIFO32_M_Data = FIFO32_M_Data, DIR=O, VEC=[0:31], BUS=MFIFO32
PORT FIFO32_M_Wr = FIFO32_M_Wr, DIR=O, BUS=MFIFO32
PORT FIFO32_M_Rem = FIFO32_M_Rem, DIR=I, VEC=[0:15], BUS=MFIFO32
-PORT downstreamReadEnable = downstreamReadEnable, DIR = O, BUS = downstream
-PORT downstreamEmpty = downstreamEmpty, DIR = I, BUS = downstream
-PORT downstreamData = downstreamData, DIR = I, BUS = downstream, VEC=[0:8]
-PORT downstreamReadClockdownstreamReadClock, DIR=O, SIGIS=Clk, BUS = downstream
-
-PORT upstreamWriteEnable = upstreamWriteEnable, DIR = O, BUS = upstream
-PORT upstreamData = upstreamData, DIR = O, BUS = upstream, VEC=[0:8]
-PORT upstreamFull = upstreamFull, DIR = I, BUS = upstream
-PORT upstreamWriteClock = upstreamWriteClock, DIR=O, SIGIS=Clk, BUS = upstream
+PORT downstreamReadEnable=downstreamReadEnable, DIR=O, BUS=downstream
+PORT downstreamEmpty=downstreamEmpty, DIR=I, BUS=downstream
+PORT downstreamData=downstreamData, DIR=I, BUS=downstream, VEC=[0:8]
+PORT downstreamReadClock=downstreamReadClock, DIR=O, SIGIS=Clk, BUS=downstream
+
+PORT upstreamWriteEnable=upstreamWriteEnable, DIR=O, BUS=upstream
+PORT upstreamData=upstreamData, DIR=O, BUS=upstream, VEC=[0:8]
+PORT upstreamFull=upstreamFull, DIR=I, BUS=upstream
+PORT upstreamWriteClock=upstreamWriteClock, DIR=O, SIGIS=Clk, BUS=upstream
PORT Rst="", DIR=I, SIGIS=Rst

0 comments on commit e2505cb

Please sign in to comment.