Skip to content

Commit 58fd161

Browse files
riktwriktw
committed
Minimal example based on simple.py for the Tang Nano 9K
1 parent fa20bf7 commit 58fd161

File tree

2 files changed

+199
-0
lines changed

2 files changed

+199
-0
lines changed

‎sipeed_tang_nano_9K_platform.py

Lines changed: 139 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,139 @@
1+
2+
#
3+
# This file is part of LiteX-Boards.
4+
#
5+
# Copyright (c) 2022 Icenowy Zheng <icenowy@aosc.io>
6+
# SPDX-License-Identifier: BSD-2-Clause
7+
8+
from migen import *
9+
10+
from litex.build.generic_platform import *
11+
from litex.build.gowin.platform import GowinPlatform
12+
from litex.build.gowin.programmer import GowinProgrammer
13+
from litex.build.openfpgaloader import OpenFPGALoader
14+
15+
16+
# IOs ----------------------------------------------------------------------------------------------
17+
18+
_io = [
19+
# Clk / Rst
20+
("clk27", 0, Pins("52"), IOStandard("LVCMOS33")),
21+
22+
# Leds
23+
("user_led", 0, Pins("10"), IOStandard("LVCMOS18")),
24+
("user_led", 1, Pins("11"), IOStandard("LVCMOS18")),
25+
("user_led", 2, Pins("13"), IOStandard("LVCMOS18")),
26+
("user_led", 3, Pins("14"), IOStandard("LVCMOS18")),
27+
("user_led", 4, Pins("15"), IOStandard("LVCMOS18")),
28+
("user_led", 5, Pins("16"), IOStandard("LVCMOS18")),
29+
30+
# Buttons.
31+
("user_btn", 0, Pins("3"), IOStandard("LVCMOS18")),
32+
("user_btn", 1, Pins("4"), IOStandard("LVCMOS18")),
33+
34+
# Serial
35+
("serial", 0,
36+
Subsignal("rx", Pins("18")),
37+
Subsignal("tx", Pins("17")),
38+
IOStandard("LVCMOS33")
39+
),
40+
41+
# SPIFlash
42+
("spiflash", 0,
43+
Subsignal("cs_n", Pins("60"), IOStandard("LVCMOS33")),
44+
Subsignal("clk", Pins("59"), IOStandard("LVCMOS33")),
45+
Subsignal("miso", Pins("62"), IOStandard("LVCMOS33")),
46+
Subsignal("mosi", Pins("61"), IOStandard("LVCMOS33")),
47+
),
48+
49+
("spisdcard", 0,
50+
Subsignal("clk", Pins("36")),
51+
Subsignal("mosi", Pins("37")),
52+
Subsignal("cs_n", Pins("38")),
53+
Subsignal("miso", Pins("39")),
54+
IOStandard("LVCMOS33"),
55+
),
56+
57+
# PSRAM
58+
("O_psram_ck", 0, Pins(2)),
59+
("O_psram_ck_n", 0, Pins(2)),
60+
("O_psram_cs_n", 0, Pins(2)),
61+
("O_psram_reset_n", 0, Pins(2)),
62+
("IO_psram_dq", 0, Pins(16)),
63+
("IO_psram_rwds", 0, Pins(2)),
64+
65+
# HDMI.
66+
("hdmi", 0,
67+
Subsignal("clk_p", Pins("69")),
68+
Subsignal("clk_n", Pins("68")),
69+
Subsignal("data0_p", Pins("71")),
70+
Subsignal("data0_n", Pins("70")),
71+
Subsignal("data1_p", Pins("73")),
72+
Subsignal("data1_n", Pins("72")),
73+
Subsignal("data2_p", Pins("75")),
74+
Subsignal("data2_n", Pins("74")),
75+
Misc("PULL_MODE=NONE"),
76+
),
77+
78+
# SPI RGB LCD.
79+
("spilcd", 0,
80+
Subsignal("reset", Pins("47")),
81+
Subsignal("cs", Pins("48")),
82+
Subsignal("clk", Pins("79")),
83+
Subsignal("mosi", Pins("77")),
84+
Subsignal("rs", Pins("47")),
85+
IOStandard("LVCMOS33"),
86+
),
87+
88+
## NEW ##
89+
#Extra GPIOs
90+
("gpio", 0, Pins("25"), IOStandard("LVCMOS33")),
91+
("gpio", 1, Pins("26"), IOStandard("LVCMOS33")),
92+
("gpio", 2, Pins("27"), IOStandard("LVCMOS33")),
93+
("gpio", 3, Pins("28"), IOStandard("LVCMOS33")),
94+
("gpio", 4, Pins("29"), IOStandard("LVCMOS33")),
95+
("gpio", 5, Pins("30"), IOStandard("LVCMOS33")),
96+
("gpio", 6, Pins("33"), IOStandard("LVCMOS33")),
97+
("gpio", 7, Pins("34"), IOStandard("LVCMOS33")),
98+
99+
#I2C!
100+
("i2c0", 0,
101+
Subsignal("sda", Pins("40")),
102+
Subsignal("scl", Pins("35")),
103+
IOStandard("LVCMOS33"),
104+
),
105+
106+
#Serial
107+
("serial0", 0,
108+
Subsignal("rx", Pins("41")),
109+
Subsignal("tx", Pins("42")),
110+
IOStandard("LVCMOS33")
111+
),
112+
]
113+
114+
# Connectors ---------------------------------------------------------------------------------------
115+
116+
_connectors = [
117+
["J6", "38 37 36 39 25 26 27 28 29 30 33 34 40 35 41 42 51 53 54 55 56 57 68 69"],
118+
["J7", "63 86 85 84 83 82 81 80 79 77 76 75 74 73 72 71 70 - 48 49 31 32 - -"],
119+
]
120+
121+
# Platform -----------------------------------------------------------------------------------------
122+
123+
class Platform(GowinPlatform):
124+
default_clk_name = "clk27"
125+
default_clk_period = 1e9/27e6
126+
127+
def __init__(self, toolchain="gowin"):
128+
GowinPlatform.__init__(self, "GW1NR-LV9QN88PC6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1NR-9C")
129+
self.toolchain.options["use_mspi_as_gpio"] = 1
130+
131+
def create_programmer(self, kit="openfpgaloader"):
132+
if kit == "gowin":
133+
return GowinProgrammer(self.devicename)
134+
else:
135+
return OpenFPGALoader(cable="ft2232")
136+
137+
def do_finalize(self, fragment):
138+
GowinPlatform.do_finalize(self, fragment)
139+
self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9/27e6)

‎sipeed_tang_nano_9k.py

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
#!/usr/bin/env python3
2+
3+
#
4+
# Minimum tang nano 9k example. Should work with most board with minimal changes
5+
#
6+
7+
import os
8+
from migen import *
9+
10+
from litex.gen import *
11+
12+
import sipeed_tang_nano_9K_platform # It can be imported from litex_boards of course, but this way changes can be kept in the same repo
13+
14+
from litex.build.io import CRG
15+
from litex.soc.integration.soc_core import *
16+
from litex.soc.integration.soc import SoCRegion
17+
from litex.soc.integration.builder import *
18+
19+
kB = 1024
20+
mB = 1024*kB
21+
22+
# BaseSoC ------------------------------------------------------------------------------------------
23+
class BaseSoC(SoCCore):
24+
def __init__(self, **kwargs):
25+
platform = sipeed_tang_nano_9K_platform.Platform()
26+
27+
sys_clk_freq = int(1e9/platform.default_clk_period)
28+
29+
# CRG --------------------------------------------------------------------------------------
30+
self.crg = CRG(platform.request(platform.default_clk_name))
31+
32+
# SoCCore ----------------------------------------------------------------------------------
33+
kwargs["integrated_rom_size"] = 64*kB
34+
kwargs["integrated_sram_size"] = 8*kB
35+
SoCCore.__init__(self, platform, sys_clk_freq, ident="Tiny LiteX SoC on Tang Nano 9K", **kwargs)
36+
37+
# Build --------------------------------------------------------------------------------------------
38+
def main():
39+
from litex.build.parser import LiteXArgumentParser
40+
parser = LiteXArgumentParser(platform=sipeed_tang_nano_9K_platform.Platform, description="Tiny LiteX SoC on Tang Nano 9K.")
41+
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
42+
args = parser.parse_args()
43+
44+
soc = BaseSoC( **parser.soc_argdict)
45+
46+
builder = Builder(soc, **parser.builder_argdict)
47+
if args.build:
48+
builder.build(**parser.toolchain_argdict)
49+
50+
if args.load:
51+
prog = soc.platform.create_programmer("openfpgaloader")
52+
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
53+
54+
if args.flash:
55+
prog = soc.platform.create_programmer("openfpgaloader")
56+
prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs")) # FIXME
57+
prog.flash(0, builder.get_bios_filename(), external=True)
58+
59+
if __name__ == "__main__":
60+
main()

0 commit comments

Comments
 (0)