In addition to Verilator and VCS software simulation testing, one can use the FireSim tool to debug faster using an FPGA. This tools comes out of the UC Berkeley Architecture Research group and is still a work in progress. You can find the documentation and website at https://fires.im/.
“Pipevew" is a useful diagnostic and visualization tool for seeing how instructions are scheduled on an out-of-order pipeline.
Pipeview displays every fetched instruction and shows when it is fetched, decoded, renamed, dispatched, issued, completed, and committed (“retired"). It shows both committed and misspeculated instructions. It also shows when stores were successfully acknowledged by the memory system (“store-completion"). It is useful for programmers who wish to see how their code is performing and for architects to see which bottlenecks are constricting machine performance.
To display the text-based pipeline visualizations, BOOM generates traces compatible with the O3 Pipeline Viewer included in the gem5 simulator suite.
To enable pipeline visualization, first set
val O3PIPEVIEW_PRINTF = true // dump trace for O3PipeView from gem5
Rebuild and rerun BOOM. You should find the traces (
vsim/output/ directories if you are using
run the core. To generate the visualization, first download and install gem5, and then run:
boom/util/pipeview-helper.py -f <TRACE_FILE> > clean_trace.out gem5/util/o3-pipeview.py --color --store_completions -o pipeview.out clean_trace.out
You can view the visualization by running:
less -r pipeview.out
To learn more about
o3-pipeview.py and to download gem5 visit