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Bug related to misaligned lr instruction #504

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JaewonHur opened this issue Nov 30, 2020 · 9 comments
Closed

Bug related to misaligned lr instruction #504

JaewonHur opened this issue Nov 30, 2020 · 9 comments

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@JaewonHur
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Type of issue: bug report

Impact: rtl refactoring

Development Phase: proposal

Other information

Misaligned load reserve instruction should not set reservation.
However boom set reservation even after misaligned load exception.

make test_p.riscv makes the bug case binary (test_p.riscv).

Logs of both boom and rocket are also included.

test.zip

@JaewonHur
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JaewonHur commented Nov 30, 2020

It seems strange.

When just misaligned lr.d and correctly aligned sc.w are executed,
the store conditional does not succeed in boom (as expected).

But if amo operation accesses the same cache line before the instructions,
sc.w succeeds (bug).

testcases.zip

@JaewonHur JaewonHur changed the title Misaligned load reserve should not set reservation Bug related to amo instructions Nov 30, 2020
@jerryz123
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Thanks for the detailed report.
Can you post a waveform from BOOM demonstrating the issue? I am having trouble reproducing the behavior.

@JaewonHur
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Attach all assembly, binary and waverforms.

tests.zip

@jerryz123
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I'm not sure what the error is here? In bug.vcd, the core appears to take an exception on a misaligned lr.d, which is expected.

@JaewonHur
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yes
'lr.d' fails as expected but the following 'sc.w' succeeds.

Following 'sc.w' should fail since 'lr.d' failed.

@jerryz123
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Oh I see, you are right, this is a bug. Sorry for the confusion.

Loads which translate successfully, but still generate exceptions, were still being fired into the L1 DCache. For normal loads this would not be an issue, as loads don't leave behind architecturally visible side effects. For LR, however, we need to specially avoid acquiring a reservation in this event.

@JaewonHur
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Thanks.
But the bug is only triggered when amo operation accesses the same cash line
before lr/sc instructions.
It should be checked.

By the way, could you confirm my other bug reports?
It seems hardfloat contains some bugs.

@jerryz123
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Any operation which caches the line of the LR will cause the misaligned LR to set a reservation, it doesn't have to be AMO.

Thanks, I will look at the floating point issues soon.

@JaewonHur
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Ah, thanks.

@JaewonHur JaewonHur changed the title Bug related to amo instructions Bug related to misaligned lr instruction Dec 1, 2020
jerryz123 added a commit that referenced this issue Mar 11, 2021
Bump spec2017 marshal workloads
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2 participants