New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Bug related to misaligned lr instruction #504
Comments
|
It seems strange. When just misaligned But if |
|
Thanks for the detailed report. |
|
Attach all assembly, binary and waverforms. |
|
I'm not sure what the error is here? In bug.vcd, the core appears to take an exception on a misaligned |
|
yes Following 'sc.w' should fail since 'lr.d' failed. |
|
Oh I see, you are right, this is a bug. Sorry for the confusion. Loads which translate successfully, but still generate exceptions, were still being fired into the L1 DCache. For normal loads this would not be an issue, as loads don't leave behind architecturally visible side effects. For LR, however, we need to specially avoid acquiring a reservation in this event. |
|
Thanks. By the way, could you confirm my other bug reports? |
|
Any operation which caches the line of the LR will cause the misaligned LR to set a reservation, it doesn't have to be AMO. Thanks, I will look at the floating point issues soon. |
|
Ah, thanks. |
Type of issue: bug report
Impact: rtl refactoring
Development Phase: proposal
Other information
Misaligned load reserve instruction should not set reservation.
However boom set reservation even after misaligned load exception.
make test_p.riscvmakes the bug case binary (test_p.riscv).Logs of both boom and rocket are also included.
test.zip
The text was updated successfully, but these errors were encountered: