Adjust operand order for vmerge and vcompress #185
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rofirrim
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Jan 12, 2023
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Looks reasonable to me.
I reckon for vmerge we followed the conditional operator (?) of C but I guess it becomes irregular with the rest of the intrinsics which adhere closely to the instruction operand order.
vcompress was likely a bit of an oversight so this one is not very controversial to me.
This makes instructions of mnemonic vvm, vxm have consistent intrinsic interface. Old: vint32m1_t vmerge_vvm_i32m1 (vbool32_t mask, vint32m1_t op1, vint32m1_t op2, size_t vl); New: vint32m1_t vmerge_vvm_i32m1 (vint32m1_t op1, vint32m1_t op2, vbool32_t selector, size_t vl); Old: vint32m1_t vcompress_vm_i32m1 (vbool32_t mask, vint32m1_t src, size_t vl); New: vint32m1_t vcompress_vm_i32m1 (vint32m1_t src, vbool32_t selector, size_t vl); Address following issues: #140 #167 Signed-off-by: eop Chen <eop.chen@sifive.com>
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Change: Rebase to latest |
eopXD
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From: vint32m1_t vmerge_vvm_i32m1 (vbool32_t mask, vint32m1_t op1, vint32m1_t op2, size_t vl); vint32m1_t vcompress_vm_i32m1 (vbool32_t mask, vint32m1_t src, size_t vl); To: vint32m1_t vmerge_vvm_i32m1 (vint32m1_t op1, vint32m1_t op2, vbool32_t selector, size_t vl); vint32m1_t vcompress_vm_i32m1 (vint32m1_t src, vbool32_t selector, size_t vl); Address issues: riscv-non-isa/rvv-intrinsic-doc#140 riscv-non-isa/rvv-intrinsic-doc#167 Pull request: riscv-non-isa/rvv-intrinsic-doc#185 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D140686
CarlosAlbertoEnciso
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Jan 13, 2023
From: vint32m1_t vmerge_vvm_i32m1 (vbool32_t mask, vint32m1_t op1, vint32m1_t op2, size_t vl); vint32m1_t vcompress_vm_i32m1 (vbool32_t mask, vint32m1_t src, size_t vl); To: vint32m1_t vmerge_vvm_i32m1 (vint32m1_t op1, vint32m1_t op2, vbool32_t selector, size_t vl); vint32m1_t vcompress_vm_i32m1 (vint32m1_t src, vbool32_t selector, size_t vl); Address issues: riscv-non-isa/rvv-intrinsic-doc#140 riscv-non-isa/rvv-intrinsic-doc#167 Pull request: riscv-non-isa/rvv-intrinsic-doc#185 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D140686
veselypeta
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Jun 12, 2024
From: vint32m1_t vmerge_vvm_i32m1 (vbool32_t mask, vint32m1_t op1, vint32m1_t op2, size_t vl); vint32m1_t vcompress_vm_i32m1 (vbool32_t mask, vint32m1_t src, size_t vl); To: vint32m1_t vmerge_vvm_i32m1 (vint32m1_t op1, vint32m1_t op2, vbool32_t selector, size_t vl); vint32m1_t vcompress_vm_i32m1 (vint32m1_t src, vbool32_t selector, size_t vl); Address issues: riscv-non-isa/rvv-intrinsic-doc#140 riscv-non-isa/rvv-intrinsic-doc#167 Pull request: riscv-non-isa/rvv-intrinsic-doc#185 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D140686
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This makes instructions of mnemonic vvm, vxm have consistent intrinsic
interface.
Before:
After:
Before:
After:
Resolves #140
Resolves #167
Corresponding changes in LLVM is posted here: