Second set of edits from AR review

cmobase/Zicbom.adoc

@@ -1,7 +1,7 @@
-[#Zicbom,reftext="Cache Block Management Instructions"]
-=== Cache Block Management Instructions
+[#Zicbom,reftext="Cache-Block Management Instructions"]
+=== Cache-Block Management Instructions
 
-Cache block management instructions enable software running on a set of coherent
+Cache-block management instructions enable software running on a set of coherent
 agents to communicate with a set of non-coherent agents by performing one of the
 following operations:
 
@@ -27,11 +27,11 @@ appear to all non-coherent agents.
 
 ****
 
-_The Zicbom extension does not prohibit observers that fall outside of the above
+_The Zicbom extension does not prohibit agents that fall outside of the above
 architectural definition; however, software cannot rely on the defined cache
-operations to have the desired effects with respect to those observers._
+operations to have the desired effects with respect to those agents._
 
-_Future extensions may define different sets of observers for the purposes of
+_Future extensions may define different sets of agents for the purposes of
 performance optimization._
 
 ****

cmobase/Zicbop.adoc

@@ -1,14 +1,11 @@
-[#Zicbop,reftext="Cache Block Prefetch Instructions"]
-=== Cache Block Prefetch Instructions
+[#Zicbop,reftext="Cache-Block Prefetch Instructions"]
+=== Cache-Block Prefetch Instructions
 
-Cache block prefetch instructions are hints to the hardware to indicate that
+Cache-block prefetch instructions are HINTs to the hardware to indicate that
 software intends to perform a particular type of memory access in the near
 future. The types of memory accesses are instruction fetch, data read (i.e.
 load), and data write (i.e. store).
 
-An implementation is not required to perform any memory accesses in response to
-a cache block prefetch instruction.
-
 The following instructions comprise the Zicbop extension:
 
 [%header,cols="^1,^1,4,8"]

cmobase/Zicboz.adoc

@@ -1,13 +1,13 @@
-[#Zicboz,reftext="Cache Block Zero Instructions"]
-=== Cache Block Zero Instructions
+[#Zicboz,reftext="Cache-Block Zero Instructions"]
+=== Cache-Block Zero Instructions
 
-Cache block zero instructions store zeros to the set of bytes corresponding to a
+Cache-block zero instructions store zeros to the set of bytes corresponding to a
 cache block. An implementation may update the bytes in any order and with any
 granularity and atomicity, including individual bytes.
 
 ****
 
-_Cache block zero instructions store zeros independent of whether data from the
+_Cache-block zero instructions store zeros independent of whether data from the
 underlying memory locations are cacheable. In addition, this specification does
 not constrain how the bytes are written._
 

cmobase/csr_state.adoc

@@ -33,7 +33,8 @@ generic format:
 Enables the execution of the cache block invalidate instruction, `CBO.INVAL`, in
 a lower privilege mode:
 
-* `00`: The instruction takes an illegal instruction exception
+* `00`: The instruction raises an illegal instruction or virtual instruction
+  exception
 * `01`: The instruction is executed and performs a flush operation
 * `10`: _Reserved_ (implementations are expected, but not required, to treat
   this value as `00`; however, software must not rely on this behavior)
@@ -44,24 +45,27 @@ a lower privilege mode:
 Enables the execution of the cache block clean instruction, `CBO.CLEAN`, and the
 cache block flush instruction, `CBO.FLUSH`, in a lower privilege mode:
 
-* `0`: The instruction takes an illegal instruction exception
+* `0`: The instruction raises an illegal instruction or virtual instruction
+  exception
 * `1`: The instruction is executed
 
 | [7]     | `CBZE`   | Cache Block Zero instruction Enable
 
 Enables the execution of the cache block zero instruction, `CBO.ZERO`, in a
 lower privilege mode:
 
-* `0`: The instruction takes an illegal instruction exception
+* `0`: The instruction raises an illegal instruction or virtual instruction
+  exception
 * `1`: The instruction is executed
 
 |===
 
 The x{csrname} registers control CMO instruction execution based on the _current
 privilege mode_ and the state of the appropriate CSRs, as detailed below.
 
-A cache block invalidate instruction executes or takes an illegal instruction
-exception based on the state of the `x{csrname}.CBIE` fields:
+A `CBO.INVAL` instruction executes or raises either an illegal instruction
+exception or a virtual instruction exception based on the state of the
+`x{csrname}.CBIE` fields:
 
 [source,sail,subs="attributes+"]
 --
@@ -107,8 +111,9 @@ either traps or performs a flush operation in a lower privileged level._
 
 ****
 
-A cache block clean or flush instruction executes or takes an illegal
-instruction exception based on the state of the `x{csrname}.CBCFE` bits:
+A `CBO.CLEAN` or `CBO.FLUSH` instruction executes or raises an illegal
+instruction or virtual instruction exception based on the state of the
+`x{csrname}.CBCFE` bits:
 
 [source,sail,subs="attributes+"]
 --
@@ -128,8 +133,8 @@ else
 
 --
 
-Finally, a cache block zero instruction executes or takes an illegal instruction
-exception based on the state of the `x{csrname}.CBZE` bits:
+Finally, a `CBO.ZERO` instruction executes or raises an illegal instruction or
+virtual instruction exception based on the state of the `x{csrname}.CBZE` bits:
 
 [source,sail,subs="attributes+"]
 --
@@ -151,10 +156,3 @@ else
 
 Each `x{csrname}` register is WARL; however, software should determine the legal
 values from the execution environment discovery mechanism.
-
-****
-
-_This specification suggests, but does not require, that implementations capture
-only legal values in the CSRs._
-
-****

cmobase/insns/cbo.clean.adoc

@@ -21,7 +21,7 @@ Encoding::
 
 Description::
 A *cbo.clean* instruction performs a clean operation on the set of coherent
-caches accessed by the observer executing the instruction.
+caches accessed by the agent executing the instruction.
 
 Operation::
 [source,sail]

cmobase/insns/cbo.flush.adoc

@@ -21,7 +21,7 @@ Encoding::
 
 Description::
 A *cbo.flush* instruction performs a flush operation on the set of coherent
-caches accessed by the observer executing the instruction.
+caches accessed by the agent executing the instruction.
 
 Operation::
 [source,sail]

cmobase/insns/cbo.inval.adoc

@@ -23,9 +23,8 @@ Encoding::
 Description::
 
 A *cbo.inval* instruction performs an invalidate operation on the set of
-coherent caches accessed by the observer executing the instruction. The
-instruction may perform a flush operation, however, depending on CSR
-programming.
+coherent caches accessed by the agent executing the instruction. The instruction
+may perform a flush operation, however, depending on CSR programming.
 
 Operation::
 [source,sail]

cmobase/insns/cbo.zero.adoc

@@ -21,10 +21,10 @@ Encoding::
 ....
 
 Description::
-A *cbo.zero* instruction performs stores to the set of bytes corresponding to a
-cache block. An implementation may or may not update the entire set of bytes
-atomically and may or may not allocate a copy of the cache block in one of the
-coherent caches accessed by the observer executing the instruction.
+
+A *cbo.zero* instruction performs stores of zeros to the set of bytes
+corresponding to a cache block. An implementation may or may not update the
+entire set of bytes atomically.
 
 Operation::
 [source,sail]

cmobase/insns/prefetch.i.adoc

@@ -2,7 +2,7 @@
 === prefetch.i
 
 Synopsis::
-Provide a hint to hardware that the cache block containing the effective address
+Provide a HINT to hardware that the cache block containing the effective address
 is likely to be accessed by an instruction fetch in the near future
 
 Mnemonic::
@@ -24,9 +24,15 @@ Encoding::
 Description::
 A *prefetch.i* instruction indicates to hardware that the cache block containing
 the effective address is likely to be accessed by an instruction fetch in the
-near future. An implementation may opt to cache a copy of the cache block in a
-cache accessed by an instruction fetch in order to improve memory access
-latency, but this behavior is _not_ required.
+near future.
+
+****
+
+_An implementation may opt to cache a copy of the cache block in a cache
+accessed by an instruction fetch in order to improve memory access latency, but
+this behavior is not required._
+
+****
 
 Operation::
 [source,sail]

cmobase/insns/prefetch.r.adoc

@@ -2,7 +2,7 @@
 === prefetch.r
 
 Synopsis::
-Provide a hint to hardware that the cache block containing the effective address
+Provide a HINT to hardware that the cache block containing the effective address
 is likely to be accessed by a data read in the near future
 
 Mnemonic::
@@ -24,9 +24,15 @@ Encoding::
 Description::
 A *prefetch.r* instruction indicates to hardware that the cache block containing
 the effective address is likely to be accessed by a data read (i.e. load) in the
-near future. An implementation may opt to cache a copy of the cache block in a
-cache accessed by a data read in order to improve memory access latency, but
-this behavior is _not_ required.
+near future.
+
+****
+
+_An implementation may opt to cache a copy of the cache block in a cache
+accessed by a data read in order to improve memory access latency, but this
+behavior is not required._
+
+****
 
 Operation::
 [source,sail]

cmobase/insns/prefetch.w.adoc

@@ -2,7 +2,7 @@
 === prefetch.w
 
 Synopsis::
-Provide a hint to hardware that the cache block containing the effective address
+Provide a HINT to hardware that the cache block containing the effective address
 is likely to be accessed by a data write in the near future
 
 Mnemonic::
@@ -24,9 +24,15 @@ Encoding::
 Description::
 A *prefetch.w* instruction indicates to hardware that the cache block containing
 the effective address is likely to be accessed by a data write (i.e. store) in
-the near future. An implementation may opt to cache a copy of the cache block in
-a cache accessed by a data write in order to improve memory access latency, but
-this behavior is _not_ required.
+the near future.
+
+****
+
+_An implementation may opt to cache a copy of the cache block in a cache
+accessed by a data write in order to improve memory access latency, but this
+behavior is not required._
+
+****
 
 Operation::
 [source,sail]