fcvt.bf16.s encoding collides with fround.h from zfa

[asb]

The Zfa extension describes fround.h as "encoded like FCVT.H.S, but with rs2=4". This collides with the proposed fcvt.bf16.s encoding which also uses 4 in the rs2 position:

field bits<32> Inst = { 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, rs1{4}, rs1{3}, rs1{2}, rs1{1}, rs1{0}, frm{2}, frm{1}, frm{0}, rd{4}, rd{3}, rd{2}, rd{1}, rd{0}, 1, 0, 1, 0, 0, 1, 1 };

[asb]

Just a ping on this.

[kdockser]

Thanks for pointing this out Alex. I'm looking into a new encoding for fcvt.bf16.s.

[kdockser]

fcvt.bf16.s is now encoded like FCVT.H.S, but with rs2=8
This will be updated in the spec soon.

[preames]

@kdockser Could I ask you to roll a new release artifact with this change and a new version number? Having a cite-able PDF with a distinct version will make it easier to do change tracking for downstream projects. In particular, this should unblock us landing experimental support in LLVM.

[kdockser]

Reopened until the change is pushed (which will be soon).

[asb]

I see the change is pushed now (thanks!), but a new PDF build and an incremented spec version number would be much appreciated. I could commit the experimental support for bfloat16 with reference to the current commit id, but it's not ideal that people wanting to review the implementation can't easily access a PDF.

[asb]

The spec number is now incremented (thanks!) - would it be possible to get a new PDF release?

[kdockser]

A new PDF has been released. This includes that changes suggested by the AR Committee.

[asb]

@kdockser I'm not seeing the new PDF? The last tagged release is https://github.com/riscv/riscv-bfloat16/releases/tag/20230322 (March 22nd)

[asb]

@kdockser I'm not seeing the new PDF? The last tagged release is https://github.com/riscv/riscv-bfloat16/releases/tag/20230322 (March 22nd)

Another ping, as the PDF still doesn't seem to be posted. Many thanks.

[asb]

It seems a new PDF was posted last week, so this request can be considered answered. Thank you.

[asb]

With the PDF now available, I've been able to update the LLVM assembler/disassembler patches based on the v0.6 version of the spec:

• [RISCV][MC] Add support for experimental Zfbfmin extension https://reviews.llvm.org/D147610
• [RISCV][MC] Add support for experimental Zvfbfmin extension https://reviews.llvm.org/D147611
• [RISCV][MC] Add support for experimental Zvfbfwma extension https://reviews.llvm.org/D147612