Skip to content
Permalink
Browse files

Add support for Ibex as a target

  • Loading branch information...
eroom1966 authored and jeremybennett committed Aug 13, 2019
1 parent a7ec31c commit 25d14e798eb4b3a54bdf22083940e78ef731b817
@@ -0,0 +1,28 @@
# Running ibex as part of the framework
# Instructions for building the target can be found in the lowRISC github repository
# Once built the frameowrk can be run as follows

# If the simulator executable is called Vibex_riscv_compliance
# define this variable including the PATH
export TARGET_SIM=/home/moore/git/lowRISCV/ibex/build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance

# define the CC prefix and target device
export RISCV_PREFIX=riscv-none-embed-
export RISCV_TARGET=ibex
export RISCV_DEVICE=rv32imc

# execute
make clean
make RISCV_ISA=rv32i
make RISCV_ISA=rv32im
make RISCV_ISA=rv32imc



#
# compare with golden
#
export RISCV_PREFIX=riscv-none-embed-
export RISCV_DEVICE=ibex_rv32imc
export RISCV_TARGET=golden
make RISCV_ISA=rv32i
@@ -0,0 +1,36 @@
// RISC-V Compliance IO Test Header File

/*
* Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied.
*
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/

#ifndef _COMPLIANCE_IO_H
#define _COMPLIANCE_IO_H

//-----------------------------------------------------------------------
// RV IO Macros (Non functional)
//-----------------------------------------------------------------------

#define RVTEST_IO_INIT
#define RVTEST_IO_WRITE_STR(_SP, _STR)
#define RVTEST_IO_CHECK()
#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)

#endif // _COMPLIANCE_IO_H
@@ -0,0 +1,51 @@
// RISC-V Compliance Test Header File
// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
// See LICENSE for license details.
//
// Description: Common header file for RV32I tests

#ifndef _COMPLIANCE_TEST_H
#define _COMPLIANCE_TEST_H

#include "riscv_test.h"

//-----------------------------------------------------------------------
// RV Compliance Macros
//-----------------------------------------------------------------------

#define TESTUTIL_BASE 0x20000
#define TESTUTIL_ADDR_HALT (TESTUTIL_BASE + 0x0)
#define TESTUTIL_ADDR_BEGIN_SIGNATURE (TESTUTIL_BASE + 0x4)
#define TESTUTIL_ADDR_END_SIGNATURE (TESTUTIL_BASE + 0x8)

#define RV_COMPLIANCE_HALT \
/* tell simulation about location of begin_signature */ \
la t0, begin_signature; \
li t1, TESTUTIL_ADDR_BEGIN_SIGNATURE; \
sw t0, 0(t1); \
/* tell simulation about location of end_signature */ \
la t0, end_signature; \
li t1, TESTUTIL_ADDR_END_SIGNATURE; \
sw t0, 0(t1); \
/* dump signature and terminate simulation */ \
li t0, 1; \
li t1, TESTUTIL_ADDR_HALT; \
sw t0, 0(t1); \
RVTEST_PASS \

#define RV_COMPLIANCE_RV32M \
RVTEST_RV32M \

#define RV_COMPLIANCE_CODE_BEGIN \
RVTEST_CODE_BEGIN \

#define RV_COMPLIANCE_CODE_END \
RVTEST_CODE_END \

#define RV_COMPLIANCE_DATA_BEGIN \
RVTEST_DATA_BEGIN \

#define RV_COMPLIANCE_DATA_END \
RVTEST_DATA_END \

#endif
@@ -0,0 +1,37 @@
IBEX = $(ROOTDIR)/riscv-target/ibex/device/rv32imc
LDSCRIPT = $(IBEX)/link.ld
TRAPHANDLER = $(IBEX)/handler.S
DEFINES = -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DTRAPHANDLER="\"$(TRAPHANDLER)\""

TARGET_SIM ?= Vibex_riscv_compliance

RUN_TARGET=\
$(TARGET_SIM) \
--term-after-cycles=100000 \
--raminit=$(work_dir_isa)/$<.vmem \
> $(work_dir_isa)/$(*).stdout \
2> $(work_dir_isa)/$@; \
grep "^SIGNATURE: " $(work_dir_isa)/$(*).stdout | sed 's/SIGNATURE: 0x//' \
> $(work_dir_isa)/$(*).signature.output

RISCV_PREFIX ?= riscv32-unknown-elf-
RISCV_GCC ?= $(RISCV_PREFIX)gcc
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
RISCV_NM ?= $(RISCV_PREFIX)nm
RISCV_READELF ?= $(RISCV_PREFIX)readelf
RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles

COMPILE_TARGET=\
$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
-I$(ROOTDIR)/riscv-test-env/ \
-I$(ROOTDIR)/riscv-test-env/p/ \
-I$(TARGETDIR)/$(RISCV_TARGET)/ \
$(DEFINES) -T$(LDSCRIPT) $$< \
-o $(work_dir_isa)/$$@; \
$$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \
$$(RISCV_READELF) -a $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.readelf; \
$$(RISCV_NM) $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.nm; \
$$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@ $(work_dir_isa)/$$@.bin; \
srec_cat $(work_dir_isa)/$$@.bin -binary -offset 0x0000 -byte-swap 4 -o $(work_dir_isa)/$$@.vmem -vmem

@@ -0,0 +1,35 @@
.section .text.trap;
.align 4;

_trap_start:
j _trap_exception
j _int_exc
j _int_exc
j _int_exc
j _int_exc
j _int_exc
j _int_exc
j _int_exc
j _int_exc
j _int_exc
j _int_exc
j _int_exc
j _int_exc


// This could be exception or user interrupt
// 0xb is the environment call to indicate the end
_trap_exception:
csrr a0, mcause;
addi a1, zero, 0xb
beq a0, a1, 1f
la a1, begin_signature
sw a0, 0(a1);
1:
la a0, write_tohost;
jr a0;

_int_exc:
la a0, write_tohost;
jr a0;

@@ -0,0 +1,71 @@
# Copyright Imperas Software Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http:#www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

Device: rv32imc
Vendor: ibex

ISA: RV32IMC
misa:
implemented: True
MXL:
range:
rangelist: [[1]]
mode: Unchanged
Extensions:
bitmask:
mask: 0x0
default: 0x1104
hw_data_misaligned_support: True
mtvec:
MODE:
range:
rangelist: [[1]]
BASE:
range:
rangelist: [[0x20000020]]

mstatus:
MPP:
range:
rangelist: [[3]]

User_Spec_Version: "2.3"
Privilege_Spec_Version: "1.11"

mvendorid:
implemented: false
marchid:
implemented: false
mimpid:
implemented: false
mhartid: 0

mcycle:
is_hardwired: true
implemented: true
minstret:
is_hardwired: true
implemented: true

## dont know how to put these in the yaml
# --override riscvOVPsim/cpu/tvec_align=0

## and then we really need to be able to put in these in the config file...:
# --override riscvOVPsim/cpu/addrbits=32
# --override riscvOVPsim/cpu/wfi_is_nop=F
# --override riscvOVPsim/cpu/tval_ii_code=T

## questions
## if misa Extensions bitmask mask is left out... the yaml defaults to zero... ovpsim does not

@@ -0,0 +1,24 @@
OUTPUT_ARCH( "riscv" )
ENTRY(_start)

SECTIONS
{
. = 0x00000000;
.text.trap : { *(.text.trap) }

. = 0x00000080;
.text.init : { *(.text.init) }

. = ALIGN(0x1000);
.tohost : { *(.tohost) }

. = ALIGN(0x1000);
.text : { *(.text) }

. = ALIGN(0x1000);
.data : { *(.data) }
.data.string : { *(.data.string)}
.bss : { *(.bss) }
_end = .;
}

@@ -0,0 +1,20 @@
# Copyright Imperas Software Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http:#www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

mtime:
implemented: False
nmi:
address: 0x800000FC # trap vec (mtvec base) + 0x7C
reset:
address: 0x80000080 # boot address + 0x80
@@ -30,7 +30,7 @@
#ifndef _COMPLIANCE_IO_H
#define _COMPLIANCE_IO_H

//#define RVTEST_IO_QUIET
#define RVTEST_IO_QUIET

//-----------------------------------------------------------------------
// RV IO Macros (Character transfer by custom instruction)
@@ -3,8 +3,12 @@ ENTRY(_start)

SECTIONS
{
. = 0x00000000;
.text.trap : { *(.text.trap) }

. = 0x80000000;
.text.init : { *(.text.init) }

. = ALIGN(0x1000);
.tohost : { *(.tohost) }
. = ALIGN(0x1000);
@@ -103,6 +103,29 @@
#define EXTRA_INIT
#define EXTRA_INIT_TIMER

//
// undefine some unusable CSR Accesses if no PRIV Mode present
//
#if defined(PRIV_MISA_S)
# if (PRIV_MISA_S==0)
# undef INIT_SPTBR
# define INIT_SPTBR
# undef INIT_PMP
# define INIT_PMP
# undef DELEGATE_NO_TRAPS
# define DELEGATE_NO_TRAPS
# undef RVTEST_ENABLE_SUPERVISOR
# define RVTEST_ENABLE_SUPERVISOR
# endif
#endif
#if defined(PRIV_MISA_U)
# if (PRIV_MISA_U==0)
# endif
#endif
#if defined(TRAPHANDLER)
#include TRAPHANDLER
#endif

#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */

#define RVTEST_CODE_BEGIN \
@@ -191,7 +214,7 @@ end_testcode: \
#define RVTEST_PASS \
RVTEST_SYNC; \
li TESTNUM, 1; \
SWSIG (0, TESTNUM); \
SWSIG (0, TESTNUM); \
ecall

#define TESTNUM gp
@@ -200,7 +223,7 @@ end_testcode: \
1: beqz TESTNUM, 1b; \
sll TESTNUM, TESTNUM, 1; \
or TESTNUM, TESTNUM, 1; \
SWSIG (0, TESTNUM); \
SWSIG (0, TESTNUM); \
ecall

//-----------------------------------------------------------------------

0 comments on commit 25d14e7

Please sign in to comment.
You can’t perform that action at this time.