From 359bedc7666742867c5708ed46db08a9ea99f55e Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Thu, 7 Dec 2023 12:02:34 -0800
Subject: [PATCH] Invalid addresses might not match. (#911)

* Clarify matching on invalid virtual addresses behavior

See:
* https://lists.riscv.org/g/tech-debug/message/1407
* https://lists.riscv.org/g/tech-debug/files/meetings%202023/2023-01-10%20Debug%20Task%20Group%20Call%20Notes.pdf
* https://lists.riscv.org/g/tech-debug/files/meetings%202023/2023-01-10%20Debug%20Task%20Group%20Call%20Slides.pdf

* Allow invalid addresses not to match at all.

Also clarify tdata2 requirements for triggers that are only used for
address matches.
---
 Sdtrig.tex             | 29 +++++++++++++++++++++++++++++
 xml/hwbp_registers.xml | 12 ------------
 2 files changed, 29 insertions(+), 12 deletions(-)

diff --git a/Sdtrig.tex b/Sdtrig.tex
index 5dc98d5c..a80fe5b0 100644
--- a/Sdtrig.tex
+++ b/Sdtrig.tex
@@ -319,6 +319,35 @@ \subsection{Cache Operations}
     \end{steps}
 \end{commentary}
 
+\subsection{Address Matches}
+
+For address matches without a mask, \RcsrTdataTwo must be able to hold all valid
+addresses in all supported translation modes. That means that after writing any
+of these valid addresses, the exact same value XLEN-wide value is read back,
+including any high bits. An implementation may be able to optimize the storage
+required, depending on the widest addresses it supports.
+
+\begin{commentary}
+    If physical addresses are less than XLEN bits wide, they are zero-extended.
+    If virtual addresses are less than XLEN bits wide, they are sign-extended.
+    \RcsrTdataTwo must be implemented with enough bits of storage to represent
+    the full range of supported physical and virtual address values when read by
+    software and used by hardware.
+\end{commentary}
+
+\subsubsection{Invalid Addresses}
+
+If \RcsrTdataTwo can hold any invalid addresses, then writes of an
+invalid address that can not be represented as-is should be converted to
+a different invalid address that can be represented.
+
+For invalid instruction fetch addresses and load and store effective addresses,
+the compare value may be changed to a different invalid address.
+
+In addition, an implementation may choose to inhibit all trigger matching
+against invalid addresses, especially if there is no support for storage of any
+invalid address values in tdata2.
+
 \section{Multiple State Change Instructions} \label{sec:multistate}
 
 An instruction that performs multiple architectural state changes (e.g.,
diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml
index 0be7746b..99b7755a 100755
--- a/xml/hwbp_registers.xml
+++ b/xml/hwbp_registers.xml
@@ -325,12 +325,6 @@
         Table~\ref{tab:hwbp_timing}, both timings should be supported on load
         address triggers.
 
-        This trigger type may be limited to address comparisons (\FcsrMcontrolSelect is
-        always 0) only. If that is the case and masking is not supported (match
-        values 4, 5, 12, 13), then \RcsrTdataTwo must be able to
-        hold all valid virtual addresses but it need not be capable of holding
-        other values.
-
         The Privileged Spec says that breakpoint exceptions that occur on
         instruction fetches, loads, or stores update the {\tt tval} CSR
         with either zero or the faulting virtual address.  The faulting
@@ -685,12 +679,6 @@
         A chain of triggers must only fire if every trigger in the chain was
         matched by the same instruction.
 
-        This trigger type may be limited to address comparisons (\FcsrMcontrolSixSelect is
-        always 0) only. If that is the case and masking is not supported (match
-        values 4, 5, 12, 13), then \RcsrTdataTwo must be able to
-        hold all valid virtual addresses but it need not be capable of holding
-        other values.
-
         The Privileged Spec says that breakpoint exceptions that occur on
         instruction fetches, loads, or stores update the {\tt tval} CSR
         with either zero or the faulting virtual address.  The faulting