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Added sbytemask field to textra32 and textra64#588

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Tim Newsome (timsifive) merged 6 commits into
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sifive:bytemask
Nov 12, 2020
Merged

Added sbytemask field to textra32 and textra64#588
Tim Newsome (timsifive) merged 6 commits into
riscv:masterfrom
sifive:bytemask

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sbytemask field in textra32 and textra64 provides byte-granular comparison of the svalue trigger value to the scontext CSR

sbytemask field in textra32 and textra64 provides byte-granular comparison of the svalue trigger value to the scontext CSR
Comment thread xml/hwbp_registers.xml Outdated
Comment thread xml/hwbp_registers.xml Outdated
Comment thread xml/hwbp_registers.xml Outdated
Bruce Ableidinger and others added 2 commits November 6, 2020 10:43
Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>
Byte masking of svalue comparison only applies when sselect==1.

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Looks good to me.

@timsifive Tim Newsome (timsifive) left a comment

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The feature looks good. I have a bunch of comments about formatting etc, however.

Comment thread xml/hwbp_registers.xml Outdated
0 (ignore).

Byte-granular comparison of the scontext CSR to the trigger's svalue in
textra32 and textra64 registers allows scontext to be defined to include

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Throughout this change, can you refer to textra32 as \RcsrTextraThirtytwo, textra64 as \RcsrTextraSixtyfour, and scontext as \RcsrScontext? Then they'll get formatted slightly different and link to the register in the doc.

Comment thread xml/hwbp_registers.xml Outdated
such as process ID and thread ID. The user can then program byte compares of
the trigger to include one or more of the contexts in the compare. For textra32
there are two byte-compare mask bits; for textra64 there are 5 byte-compare mask bits.
Byte masking only applies to scontext comparison; i.e when sselect==1.

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when \FcsrTextraThirtytwoSselect is 1 instead of when sselect==1.

Comment thread xml/hwbp_registers.xml Outdated
Comment on lines +970 to +971
Byte-granular comparison of the scontext CSR to the trigger's svalue in
textra32 and textra64 registers allows scontext to be defined to include

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This text is part of the description of textra32. It should probably be repeated in the textra64 section, in which case you don't need to mention the register name at all. E.g. "Byte-granular comparison of \RcsrScontext to \FcsrTextraThirtytwoSvalue allows \RcsrScontext to be defined to include ..."

Comment thread xml/hwbp_registers.xml Outdated
Comment on lines +1002 to +1004
0=compare, 1=don't compare byte, i.e. byte is masked out
bit 18 = lower byte compare of svalue (bits [7:0])
bit 19 = upper byte compare of svalue (bits [15:8])

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We use capitalization and punctuation in field descriptions. When mentioning the behavior of values we use : instead of = (see e.g. https://github.com/riscv/riscv-debug-spec/blob/master/xml/dm_registers.xml#L12).

I don't think we have any examples yet of where each bit inside a field has a different meaning. The closest is hawindow, where we say "I.e. bit 0 refers to hart $\RdmHawindowsel * 32$, while bit 31 refers to hart $\RdmHawindowsel * 32 + 31$." (https://github.com/riscv/riscv-debug-spec/blob/master/xml/dm_registers.xml#L347).

Putting that all together, I think we want language like:
When the least-significant bit of this field is 1, it causes bits 7:0 in the comparison to be ignored when \FcsrTextraThirtytwoSselect=1. When the next most significant bit of this field is 1, causes bits 15:8 to be ignored in the comparison when \FcsrTextraThirtytwoSselect=1, and so on.

Comment thread xml/hwbp_registers.xml Outdated
<field name="0" bits="47:41" access="R" reset="0" />

<field name="sbytemask" bits="40:36" access="WARL" reset="0">
0=compare, 1=don't compare, i.e byte compare is masked out

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Same as above.

Comment thread xml/hwbp_registers.xml Outdated
Comment on lines +1006 to +1007
Byte masking of svalue only applies to scontext comparison; i.e.
when sselect==1.

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I think I mentioned that adequately in my suggestion enough. If not, use \FcsrTextraThirtytwoSselect=1 instead of sselect==1.

Tim Newsome (timsifive) added a commit that referenced this pull request Nov 10, 2020
We used to not do this because those fields would often have the same
name as some other field, and there was a name collision. Now however we
have long, fully qualified names. This change is needed for #588 which
references \FcsrTextraSixtyfourSselect.
Comment thread xml/hwbp_registers.xml Outdated
tie any number of upper bits to 0. The $|select|$ bits may only support
0 (ignore).

Byte-granular comparison of the \RcsrScontext to \FcsrTextraThirtytwoSvalue

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Just "\RcsrScontext" instead of "the \RcsrScontext"

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This paragraph should refer to \FcsrTextraThirtytwoSbytemask since that is what implements the comparison.

Comment thread xml/hwbp_registers.xml Outdated
For example, software instrumentation can program the \RcsrScontext value to be
the concatenation of different ID contexts such as process ID and thread ID.
The user can then program byte compares to include one or more of the contexts
in the compare. For \RcsrTextraThirtytwo there are two byte-compare mask bits.

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No need to talk explicitly about textra32 because this paragraph is in the section that defines textra32, and the size is already clear from the figure that is placed directly below this block of text.

Comment thread xml/hwbp_registers.xml Outdated
When the least significant bit of this field is 1, it causes bits 7:0
in the comparison to be ignored, when \FcsrTextraThirtytwoSselect=1.
When the next most significant bit of this field is 1, it causes bits 15:8
to be ignored in the comparison, when \FcsrTextraThirtytwoSselect=1

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Needs a period at the end of the sentence.

Comment thread xml/hwbp_registers.xml Outdated
5, or 6 and XLEN=64. The fields are defined
above, in \RcsrTextraThirtytwo.

Byte-granular comparison of the \RcsrScontext to \FcsrTextraSixtyfourSvalue in

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Same feedback as textra32 version.

Comment thread xml/hwbp_registers.xml Outdated
When the least significant bit of this field is 1, it causes bits 7:0
in the comparison to be ignored, when \FcsrTextraSixtyfourSselect=1.
When the next most significant bit of this field is 1, it causes bits 15:8
to be ignored in the comparison, when \FcsrTextraSixtyfourSselect=1

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Need a period at the end of these sentences.

Comment thread xml/hwbp_registers.xml Outdated
Comment on lines +1057 to +1060
When the next most significant bit of this field is 1, it causes bits 31:24
to be ignored in the comparison, when \FcsrTextraSixtyfourSselect=1
When the next most significant bit of this field is 1, it causes bits 33:32
to be ignored in the comparison, when \FcsrTextraSixtyfourSselect=1

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At some point we'll have to find a nicer way to write this, but I don't have any good ideas right now. Probably can merge like this and fix it later.

Tim Newsome (timsifive) added a commit that referenced this pull request Nov 11, 2020
We used to not do this because those fields would often have the same
name as some other field, and there was a name collision. Now however we
have long, fully qualified names. This change is needed for #588 which
references \FcsrTextraSixtyfourSselect.

@timsifive Tim Newsome (timsifive) left a comment

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Looks good, except for the typo.

I think it still won't pass the checks even with this fix because it depends on #591. You can fix this in your PR by merging latest master into your bytemask branch, but I'm OK skipping that step and just merging this once the typo is fixed.

Comment thread xml/hwbp_registers.xml Outdated
allows \RcsrScontext to be defined to include more than one element of comparison.
For example, software instrumentation can program the \RcsrScontext value to be
the concatenation of different ID contexts such as process ID and thread ID.
The user can then program byte compares based on \FcsrTextraThritytwoSbytemask

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Typo: FcsrTextraThritytwoSbytemask -> FcsrTextraThirtytwoSbytemask

@timsifive Tim Newsome (timsifive) left a comment

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I'll merge this tomorrow, unless there is more discussion.

@timsifive Tim Newsome (timsifive) merged commit 53191a4 into riscv:master Nov 12, 2020
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3 participants