add dmstatus.ndmresetpending to allow a debugger to determine when ndmreset is complete#594
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timsifive merged 4 commits intoNov 16, 2020
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ernie-sifive
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This change looks fine to me.
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Nov 11, 2020
Co-authored-by: Tim Newsome <tim@sifive.com>
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Currently there is a well-defined way for a debugger to determine when reset has begun and completed for any arbitrary subset of harts (most recently discussed in PR 480, 494). However the system as a whole is composed of more than just the harts, and there is no overarching “havendmreset” signal analogous to the per-hart “havereset” signals to indicate when this state outside of the harts has completed reset.
Because some system state accessible to a debugger (for example, peripherals' register space via SBA) can continue to be in reset after all harts in a system have completed reset, it is useful for the debugger to know when ndmreset is still happening and when it has completed.
This PR implements a way for a debugger to determine if ndmreset has completed on implementations that choose to support the feature. It proposes to use a bit of dmstatus called ndmresetpending that can be asserted by a debug module at the start of ndmreset and deasserted when ndmreset is complete. Hardware that does not implement this feature leaves the bit hardwired zero (as prior to this PR), and a debugger is not required to read the bit, in order to maintain backward compatibility.
The proposal also has the ndmresetpending bit return a value of 1 on reads whenever ndmreset is 1. This part of the proposal is in place to allow a debugger to detect whether the feature is supported without requiring a separate 'capabilities' bit or breaking backward compatibility. Therefore, the prescription for using this feature is: when requesting ndmreset,
so debuggers not wanting to use this feature have no change to present behavior.