From cc901cfb8a574291f494a275b4930adbecb30f09 Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Wed, 18 Oct 2023 13:06:05 -0700
Subject: [PATCH] AR: Comment itrigger limited to 32 ints if XLEN=32

Resolves #904.
---
 xml/hwbp_registers.xml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml
index 1c63843a..292e5a16 100755
--- a/xml/hwbp_registers.xml
+++ b/xml/hwbp_registers.xml
@@ -1141,6 +1141,14 @@
         In addition the trigger can be enabled for non-maskable interrupts using
         \FcsrItriggerNmi.
 
+        \begin{commentary}
+        If XLEN is 32, then it is not possible to set a trigger for interrupts
+        with Exception Code larger than 31. A future version of the RISC-V
+        Privileged Spec will likely define interrupt Exception Codes 32 through
+        47. Some of those numbers are already being used by the RISC-V Advanced
+        Interrupt Architecture.
+        \end{commentary}
+
         Hardware may only support a subset of interrupts for this trigger.  A
         debugger must read back \RcsrTdataTwo after writing it to confirm the
         requested functionality is actually supported.