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Fix MODE field description in the mtvec register

In Section 1.6, "Exceptions, Traps, and Interrupts" of the unprivileged
specification, a distinction is made between exceptions and interrupts.

Table 13 in the privileged specification uses the term "exceptions" as a
catch-all expression, encompassing both "exceptions and interrupts"
which may not be immediately apparent.

Reading "exceptions" merely as "exceptions" initially led me to believe
that the 0th bit is used to control exception handling behavior, while
the 1st bit is used to control interrupt handling behavior.

Signed-off-by: Andrei Solodovnikov <VoultBoy@yandex.ru>
b0040f3

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RISC-V Instruction Set Manual

RISC-V ISA Build

This repository contains the source files for the RISC-V Instruction Set Manual, which consists of the Privileged RISC-V Instruction Set Manual (LaTeX) and the Unprivileged RISC-V Instruction Set Manual (AsciiDoc). The preface of each document indicates the version of each standard that has been formally ratified by RISC-V International.

This work is licensed under a Creative Commons Attribution 4.0 International License. See the LICENSE file for details.

The RISC-V Instruction Set Manual is organized into the following volumes:

  • Volume I: User-Level ISA
  • Volume II: Privileged Architecture

Official and Draft Versions

The canonical list of open-source RISC-V implementations' marchid CSR values is available in the marchid.md file.

Contributing

If you would like to contribute to this documentation, please refer to the Documentation Developer's Guide.

The recommended method for building the PDF files is to use the Docker Image, as described in the RISC-V Docs Base Container Image repository.

Alternative build methods, such as local builds and GitHub Action builds, are also available and described in the Documentation Developer's Guide.