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Revert "Fix inconsistency between RVC text and opcode table"

This reverts commit 272d038.
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aswaterman committed May 4, 2018
1 parent be663ae commit 01190b6ebeb29cfac6783a3e7ce30cd529bf6c59
Showing with 6 additions and 3 deletions.
  1. +3 −0 src/c.tex
  2. +3 −3 src/rvc-instr-table.tex
@@ -389,16 +389,19 @@ \subsection*{Stack-Pointer-Based Loads and Stores}
C.LWSP loads a 32-bit value from memory into register {\em rd}. It computes
an effective address by adding the {\em zero}-extended offset, scaled by 4, to
the stack pointer, {\tt x2}. It expands to {\tt lw rd, offset[7:2](x2)}.
C.LWSP is only valid when $\textit{rd}{\neq}\texttt{x0}$.

C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into
register {\em rd}. It computes its effective address by adding the
zero-extended offset, scaled by 8, to the stack pointer, {\tt x2}.
It expands to {\tt ld rd, offset[8:3](x2)}.
C.LDSP is only valid when $\textit{rd}{\neq}\texttt{x0}$.

C.LQSP is an RV128C-only instruction that loads a 128-bit value from memory
into register {\em rd}. It computes its effective address by adding the
zero-extended offset, scaled by 16, to the stack pointer, {\tt x2}.
It expands to {\tt lq rd, offset[9:4](x2)}.
C.LQSP is only valid when $\textit{rd}{\neq}\texttt{x0}$.

C.FLWSP is an RV32FC-only instruction that loads a single-precision
floating-point value from memory into floating-point register {\em rd}. It
@@ -427,15 +427,15 @@
\multicolumn{1}{c|}{uimm[5]} &
\multicolumn{5}{c|}{rd$\neq$0} &
\multicolumn{5}{c|}{uimm[4$\vert$9:6]} &
\multicolumn{2}{c|}{10} & C.LQSP {\em \tiny (RV128)} \\
\multicolumn{2}{c|}{10} & C.LQSP {\em \tiny (RV128; RES, rd=0)} \\
\whline{2-17}

&
\multicolumn{3}{|c|}{010} &
\multicolumn{1}{c|}{uimm[5]} &
\multicolumn{5}{c|}{rd$\neq$0} &
\multicolumn{5}{c|}{uimm[4:2$\vert$7:6]} &
\multicolumn{2}{c|}{10} & C.LWSP \\
\multicolumn{2}{c|}{10} & C.LWSP {\em \tiny (RES, rd=0)} \\
\whline{2-17}

&
@@ -451,7 +451,7 @@
\multicolumn{1}{c|}{uimm[5]} &
\multicolumn{5}{c|}{rd$\neq$0} &
\multicolumn{5}{c|}{uimm[4:3$\vert$8:6]} &
\multicolumn{2}{c|}{10} & C.LDSP {\em \tiny (RV64/128)} \\
\multicolumn{2}{c|}{10} & C.LDSP {\em \tiny (RV64/128; RES, rd=0)} \\
\whline{2-17}

&

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