FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum

src/f.tex

@@ -271,13 +271,6 @@ \section{NaN Generation and Propagation}
 single-precision floating-point, this corresponds to the pattern {\tt
 0x7fc00000}.
 
-For FMIN and FMAX, if at least one input is a signaling NaN, or if both inputs
-are quiet NaNs, the result is the canonical NaN.  If one operand is a quiet NaN
-and the other is not a NaN, the result is the non-NaN operand.
-
-The sign-injection instructions (FSGNJ, FSGNJN, FSGNJX) do not canonicalize
-NaNs; they manipulate the underlying bit patterns directly.
-
 \begin{commentary}
 We considered propagating NaN payloads, as is recommended by the standard,
 but this decision would have increased hardware cost.  Moreover, since this
@@ -374,9 +367,8 @@ \section{Single-Precision Floating-Point Computational Instructions}
 R-type format with the OP-FP major opcode.  FADD.S, FSUB.S,
 FMUL.S, and FDIV.S perform single-precision floating-point addition,
 subtraction, multiplication, and division, respectively, between {\em rs1} and
-{\em rs2}, writing the result to {\em rd}.  FMIN.S and FMAX.S
-write, respectively, the smaller or larger of {\em rs1} and {\em rs2} to {\em
-rd}.  FSQRT.S computes the square root of {\em rs1} and writes the
+{\em rs2}, writing the result to {\em rd}.
+FSQRT.S computes the square root of {\em rs1} and writes the
 result to {\em rd}.
 
 The 2-bit floating-point format field {\em fmt} is encoded as shown in
@@ -408,6 +400,14 @@ \section{Single-Precision Floating-Point Computational Instructions}
 rounding mode using the {\em rm} field with the encoding shown in
 Table~\ref{rm}.
 
+Floating-point minimum-number and maximum-number instructions FMIN.S and
+FMAX.S write, respectively, the smaller or larger of {\em rs1} and {\em rs2}
+to {\em rd}.  For the purposes of these instructions only, the value $-0.0$ is
+considered to be less than the value $+0.0$.  If both inputs are NaNs, the
+result is the canonical NaN.  If only one operand is a NaN, the result is the
+non-NaN operand.  Signaling NaN inputs raise the invalid operation exception,
+even when the result is not NaN.
+
 \vspace{-0.2in}
 \begin{center}
 \begin{tabular}{R@{}F@{}R@{}R@{}F@{}R@{}O}
@@ -431,8 +431,8 @@ \section{Single-Precision Floating-Point Computational Instructions}
 5 & 2 & 5 & 5 & 3 & 5 & 7 \\
 FADD/FSUB & S & src2 & src1 & RM  & dest & OP-FP  \\
 FMUL/FDIV & S & src2 & src1 & RM  & dest & OP-FP  \\
-FMIN-MAX  & S & src2 & src1 & MIN/MAX & dest & OP-FP  \\
 FSQRT     & S & 0    & src  & RM  & dest & OP-FP  \\
+FMIN-MAX  & S & src2 & src1 & MIN/MAX & dest & OP-FP  \\
 \end{tabular}
 \end{center}
 
@@ -560,7 +560,8 @@ \section{Single-Precision Floating-Point Conversion and Move \mbox{Instructions}
   rs2}'s sign bit; for FSGNJN, the result's sign bit is the opposite
 of {\em rs2}'s sign bit; and for FSGNJX, the sign bit is the XOR of
 the sign bits of {\em rs1} and {\em rs2}.  Sign-injection instructions
-do not set floating-point exception flags.  Note, FSGNJ.S {\em rx, ry,
+do not set floating-point exception flags, nor do they canonicalize
+NaNs.  Note, FSGNJ.S {\em rx, ry,
   ry} moves {\em ry} to {\em rx} (assembler pseudo-op FMV.S {\em rx,
   ry}); FSGNJN.S {\em rx, ry, ry} moves the negation of {\em ry} to
 {\em rx} (assembler pseudo-op FNEG.S {\em rx, ry}); and FSGNJX.S {\em rx,

src/preface.tex

@@ -1,6 +1,58 @@
 \chapter{Preface}
 
-This is version \specrev\ of the document describing the RISC-V
+This is {\bf a draft of} version 2.3 of the document describing the RISC-V
+user-level architecture.  The document contains the following
+versions of the RISC-V ISA modules:
+\begin{table}[hbt]
+  \centering
+  \begin{tabular}{|c|l|c|}
+    \hline
+    Base     & Version & Frozen? \\
+    \hline
+    RV32I    & 2.0 & Y \\
+    RV32E    & 1.9 & N \\
+    RV64I    & 2.0 & Y \\
+    RV128I   & 1.7 & N \\
+    \hline
+    Extension & Version & Frozen? \\
+    \hline
+    M        & 2.0 & Y \\
+    A        & 2.0 & Y \\
+    F        & 2.0 & Y \\
+    D        & 2.0 & Y \\
+    Q        & 2.0 & Y \\
+    L        & 0.0 & N \\
+    C        & 2.0 & Y \\
+    B        & 0.0 & N \\
+    J        & 0.0 & N \\
+    T        & 0.0 & N \\
+    P        & 0.1 & N \\
+    V        & 0.2 & N \\
+    N        & 1.1 & N \\
+    \hline
+  \end{tabular}
+\end{table}
+
+To date, no parts of the standard have been officially ratified by the
+RISC-V Foundation, but the components labeled ``frozen'' above are not
+expected to change during the ratification process beyond resolving
+ambiguities and holes in the specification.
+
+The major changes in this version of the document include:
+\begin{itemize}
+\parskip 0pt
+\itemsep 1pt
+\item Improvements to the description and commentary.
+\item Defined the signed-zero behavior of FMIN.{\em fmt} and FMAX.{\em fmt},
+  and changed their behavior on signaling-NaN inputs to conform to the
+  minimumNumber and maximumNumber operations in the proposed IEEE 754-201x
+  specification.
+\end{itemize}
+~\\
+
+\section*{Preface to Document Version 2.2}
+
+This is version 2.2 of the document describing the RISC-V
 user-level architecture.  The document contains the following
 versions of the RISC-V ISA modules:
 \begin{table}[hbt]