From edf9bb7da3737b965b99e6c36006489cf0e1b7bd Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 20:28:10 -0500 Subject: [PATCH 01/20] Update register name order https://github.com/riscv/riscv-isa-manual/issues/1352 Signed-off-by: Kersten Richter --- src/supervisor.adoc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/supervisor.adoc b/src/supervisor.adoc index 636c3bf32..e87fbdd7d 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -36,7 +36,7 @@ supervisor-level CSR descriptions. ==== [[sstatus]] -==== Supervisor Status Register (`sstatus`) +==== Supervisor Status (`sstatus`) Register The `sstatus` register is an SXLEN-bit read/write register formatted as shown in <> when SXLEN=32 @@ -176,7 +176,7 @@ of one endianness to execute user-mode programs of the opposite endianness. ==== -==== Supervisor Trap Vector Base Address Register (`stvec`) +==== Supervisor Trap Vector Base Address(`stvec`) Register The `stvec` register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a @@ -217,7 +217,7 @@ supervisor-mode timer interrupt (see <>) causes the `pc` to be set to BASE+`0x14`. Setting MODE=Vectored may impose a stricter alignment constraint on BASE. -==== Supervisor Interrupt Registers (`sip` and `sie`) +==== Supervisor Interrupt (`sip` and `sie`) Registers The `sip` register is an SXLEN-bit read/write register containing information on pending interrupts, while `sie` is the corresponding @@ -336,7 +336,7 @@ the counter values. The implementation must provide a facility for scheduling timer interrupts in terms of the real-time counter, `time`. -==== Counter-Enable Register (`scounteren`) +==== Counter-Enable (`scounteren`) Register .Counter-enable register (`scounteren`) include::images/bytefield/scounteren.edn[] @@ -364,7 +364,7 @@ access a counter if the corresponding bits in `scounteren` and `mcounteren` are both set. ==== -==== Supervisor Scratch Register (`sscratch`) +==== Supervisor Scratch (`sscratch`) Register The `sscratch` register is an SXLEN-bit read/write register, dedicated for use by the supervisor. Typically, `sscratch` is used to hold a @@ -375,7 +375,7 @@ with a user register to provide an initial working register. .Supervisor Scratch Register include::images/bytefield/sscratch.edn[] -==== Supervisor Exception Program Counter (`sepc`) +==== Supervisor Exception Program Counter (`sepc`) Register `sepc` is an SXLEN-bit read/write register formatted as shown in <>. The low bit of `sepc` (`sepc[0]`) is always zero. On implementations that support only IALIGN=32, the two low bits (`sepc[1:0]`) are always zero. @@ -402,7 +402,7 @@ though it may be explicitly written by software. include::images/bytefield/epcreg.edn[] [[scause]] -==== Supervisor Cause Register (`scause`) +==== Supervisor Cause (`scause`) Register The `scause` register is an SXLEN-bit read-write register formatted as shown in <>. When a trap is taken into @@ -583,7 +583,7 @@ instruction bits is implemented, `stval` must also be able to hold all values less than latexmath:[$2^N$], where latexmath:[$N$] is the smaller of SXLEN and ILEN. -==== Supervisor Environment Configuration Register (`senvcfg`) +==== Supervisor Environment Configuration (`senvcfg`) Register The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as shown in <>, that controls certain @@ -2132,7 +2132,7 @@ QoS Register Interface (CBQRI) specification, which provides methods for setting resource usage limits and monitoring resource consumption. The `RCID` controls resource allocations, while the `MCID` is used for tracking resource usage. -=== Supervisor Resource Management Configuration register +=== Supervisor Resource Management Configuration (`srmcfg`) register The `srmcfg` register is an SXLEN-bit read/write register used to configure a Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). Both `RCID` From 7eb7f9531a8248670355dcfca94206c8757d3bda Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 20:40:46 -0500 Subject: [PATCH 02/20] Update machine.adoc Signed-off-by: Kersten Richter --- src/machine.adoc | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/machine.adoc b/src/machine.adoc index 2745dac4c..7e4e15c88 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -16,7 +16,7 @@ In addition to the machine-level CSRs described in this section, M-mode code can access all CSRs at lower privilege levels. [[misa]] -==== Machine ISA Register `misa` +==== Machine ISA (`misa`) Register The `misa` CSR is a *WARL* read-write register reporting the ISA supported by the hart. This register must be readable in any implementation, but a value of zero can be returned to indicate the `misa` register has not been implemented, requiring that CPU capabilities be determined through a separate non-standard mechanism. @@ -239,7 +239,7 @@ corresponding feature is not implemented. This follows from the fact that, when a feature is not implemented, the corresponding opcodes and CSRs become reserved, not necessarily illegal. -==== Machine Vendor ID Register `mvendorid` +==== Machine Vendor ID (`mvendorid`) Register The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. This register must be @@ -276,7 +276,7 @@ manufacturer ID standard. At time of writing, registering a manufacturer ID with JEDEC has a one-time cost of $500. ==== -==== Machine Architecture ID Register `marchid` +==== Machine Architecture ID (`marchid`) Register The `marchid` CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart. This register must be readable in any @@ -315,7 +315,7 @@ organization. The `misa` register also helps distinguish different variants of a design. ==== -==== Machine Implementation ID Register `mimpid` +==== Machine Implementation ID (`mimpid`) Register The `mimpid` CSR provides a unique encoding of the version of the processor implementation. This register must be readable in any @@ -336,7 +336,7 @@ most-significant nibble down) with subfields aligned on nibble boundaries to ease human readability. ==== -==== Hart ID Register `mhartid` +==== Hart ID (`mhartid`) Register The `mhartid` CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. This register must @@ -357,7 +357,7 @@ For efficiency, system implementers should aim to reduce the magnitude of the largest hart ID used in a system. ==== -==== Machine Status Registers (`mstatus` and `mstatush`) +==== Machine Status (`mstatus` and `mstatush`) Registers The `mstatus` register is an MXLEN-bit read/write register formatted as shown in <> for RV32 and @@ -1067,7 +1067,7 @@ their context to be saved and restored to service asynchronous interrupts, unless the interrupt results in a user-level context swap. ==== -==== Machine Trap-Vector Base-Address Register (`mtvec`) +==== Machine Trap-Vector Base-Address (`mtvec`) Register The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds trap vector configuration, consisting of a vector base address (BASE) @@ -1132,7 +1132,7 @@ implemented without a hardware adder circuit. Reset and NMI vector locations are given in a platform specification. ==== -==== Machine Trap Delegation Registers (`medeleg` and `mideleg`) +==== Machine Trap Delegation (`medeleg` and `mideleg`) Registers By default, all traps at any privilege level are handled in machine mode, though a machine-mode handler can redirect traps back to the @@ -1226,7 +1226,7 @@ For exceptions that cannot occur in less privileged modes, the corresponding `medeleg` bits should be read-only zero. In particular, `medeleg`[11] is read-only zero. -==== Machine Interrupt Registers (`mip` and `mie`) +==== Machine Interrupt (`mip` and `mie`) Registers The `mip` register is an MXLEN-bit read/write register containing information on pending interrupts, while `mie` is the corresponding @@ -1452,7 +1452,7 @@ only bits 63-32. The `mhpmevent__n__h` CSRs are provided only if the Sscofpmf extension is implemented. [[mcounteren]] -==== Machine Counter-Enable Register (`mcounteren`) +==== Machine Counter-Enable (`mcounteren`) Register The counter-enable register `mcounteren` is a 32-bit register that controls the availability of the hardware performance-monitoring @@ -1504,7 +1504,7 @@ corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. In harts without U-mode, the `mcounteren` register should not exist. -==== Machine Counter-Inhibit CSR (`mcountinhibit`) +==== Machine Counter-Inhibit (`mcountinhibit`) Register .Counter-inhibit register `mcountinhibit` include::images/bytefield/counterinh.adoc[] @@ -1538,7 +1538,7 @@ Because the `time` counter can be shared between multiple cores, it cannot be inhibited with the `mcountinhibit` mechanism. ==== -==== Machine Scratch Register (`mscratch`) +==== Machine Scratch (`mscratch`) Register The `mscratch` register is an MXLEN-bit read/write register dedicated for use by machine mode. Typically, it is used to hold a pointer to a @@ -1602,7 +1602,7 @@ though it may be explicitly written by software. include::images/bytefield/mepcreg.adoc[] [[mcause]] -==== Machine Cause Register (`mcause`) +==== Machine Cause (`mcause`) Register The `mcause` register is an MXLEN-bit read-write register formatted as shown in <>. When a trap is taken into @@ -1864,7 +1864,7 @@ occurrence is generally expected to be recognized at the point in the overall priority order at which the hardware error is discovered. ==== -==== Machine Trap Value Register (`mtval`) +==== Machine Trap Value (`mtval`) Register The `mtval` register is an MXLEN-bit read-write register formatted as shown in <>. When a trap is taken into @@ -1954,7 +1954,7 @@ return the faulting instruction bits is implemented, `mtval` must also be able to hold all values less than 2^__N__^, where _N_ is the smaller of MXLEN and ILEN. -==== Machine Configuration Pointer Register (`mconfigptr`) +==== Machine Configuration Pointer (`mconfigptr`) Register `mconfigptr` is an MXLEN-bit read-only CSR, formatted as shown in <>, that holds the physical @@ -1991,7 +1991,7 @@ M-mode software towards the beginning of the boot process. ==== [[sec:menvcfg]] -==== Machine Environment Configuration Register (`menvcfg`) +==== Machine Environment Configuration (`menvcfg`) Register The `menvcfg` CSR is a 64-bit read/write register, formatted as shown in <>, that controls @@ -2098,7 +2098,7 @@ Register `menvcfgh` does not exist when XLEN=64. If U-mode is not supported, then registers `menvcfg` and `menvcfgh` do not exist. -==== Machine Security Configuration Register (`mseccfg`) +==== Machine Security Configuration (`mseccfg`) Register `mseccfg` is an optional 64-bit read/write register, formatted as shown in <>, that controls security features. @@ -2125,7 +2125,7 @@ Register `mseccfgh` does not exist when XLEN=64. === Machine-Level Memory-Mapped Registers -==== Machine Timer Registers (`mtime` and `mtimecmp`) +==== Machine Timer (`mtime` and `mtimecmp`) Registers Platforms provide a real-time counter, exposed as a memory-mapped machine-mode read-write register, `mtime`. `mtime` must increment at From 85e1d20c52849ca8f6157add4f020abc0dc94d0d Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 20:47:01 -0500 Subject: [PATCH 03/20] Update sstc.adoc Signed-off-by: Kersten Richter --- src/sstc.adoc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/sstc.adoc b/src/sstc.adoc index a96ea877e..5c72adaca 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -27,7 +27,7 @@ and the VS-level vstimecmp CSR. === Machine and Supervisor Level Additions -==== *Supervisor Timer Register (stimecmp)* +==== Supervisor Timer (stimecmp) Register This extension adds this new CSR. @@ -66,7 +66,7 @@ existing S-mode software that uses this SEE facility, while new S-mode software takes advantage of stimecmp directly.) ==== -==== Machine Interrupt Registers (mip and mie) +==== Machine Interrupt (mip and mie) Registers This extension modifies the description of the STIP/STIE bits in these registers as follows: @@ -80,7 +80,7 @@ implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp. This timer interrupt signal is cleared by writing stimecmp with a value greater than the current time value. -==== Supervisor Interrupt Registers (sip and sie) +==== Supervisor Interrupt (sip and sie) Registers This extension modifies the description of the STIP/STIE bits in these registers as follows: @@ -94,7 +94,7 @@ interrupts generated by stimecmp, is set and cleared by writing stimecmp with a value that respectively is less than or equal to, or greater than, the current time value. -==== Machine Counter-Enable Register (mcounteren) +==== Machine Counter-Enable (mcounteren) Register This extension adds to the description of the TM bit in this register as follows: @@ -109,7 +109,7 @@ hcounteren. === Hypervisor Extension Additions -==== *Virtual Supervisor Timer Register (vstimecmp)* +==== Virtual Supervisor Timer (vstimecmp) Register This extension adds this new CSR. @@ -141,7 +141,7 @@ ensures compatibility with existing guest VS-mode software that uses this SEE facility, while new VS-mode software takes advantage of vstimecmp directly.) ==== -==== Hypervisor Interrupt Registers (hvip, hip, and hie) +==== Hypervisor Interrupt (hvip, hip, and hie) Registers This extension modifies the description of the VSTIP/VSTIE bits in the hip/hie registers as follows: @@ -155,7 +155,7 @@ vstimecmp with a value that respectively is less than or equal to, or greater than, the current (time + htimedelta) value. The hip.VSTIP bit remains defined while V=0 as well as V=1. -==== Hypervisor Counter-Enable Register (hcounteren) +==== Hypervisor Counter-Enable (hcounteren) Register This extension adds to the description of the TM bit in this register as follows: From daec285c0652485f5b829023589430aaaf90ef2a Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 20:47:53 -0500 Subject: [PATCH 04/20] Update sscofpmf.adoc Signed-off-by: Kersten Richter --- src/sscofpmf.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc index 7eb8cf297..4d301d579 100644 --- a/src/sscofpmf.adoc +++ b/src/sscofpmf.adoc @@ -101,7 +101,7 @@ maintaining a bit mask reflecting which counters are active and due to eventually overflow. ==== -=== Supervisor Count Overflow (scountovf) CSR +=== Supervisor Count Overflow (scountovf) Register This extension adds the `scountovf` CSR, a 32-bit read-only register that contains shadow copies of From 2d0f1757f0f47c12c26787692994d6889c1fb2c5 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 21:18:18 -0500 Subject: [PATCH 05/20] Update hypervisor.adoc Signed-off-by: Kersten Richter --- src/hypervisor.adoc | 62 ++++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index d0edb9b24..09d70a2b4 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -158,7 +158,7 @@ In this chapter, we use the term _HSXLEN_ to refer to the effective XLEN when executing in HS-mode, and _VSXLEN_ to refer to the effective XLEN when executing in VS-mode. -==== Hypervisor Status Register (`hstatus`) +==== Hypervisor Status (`hstatus`) Register The `hstatus` register is an HSXLEN-bit read/write register formatted as shown in <> when HSXLEN=32 @@ -270,7 +270,7 @@ to VS-level memory management data structures, such as page tables. An implementation may make VSBE a read-only field that always specifies the same endianness as HS-mode. -==== Hypervisor Trap Delegation Registers (`hedeleg` and `hideleg`) +==== Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers Register `hedeleg` is a 64-bit read/write register, formatted as shown in <>. @@ -396,7 +396,7 @@ Store/AMO guest-page fault |=== [[hinterruptregs]] -==== Hypervisor Interrupt Registers (`hvip`, `hip`, and `hie`) +==== Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers Register `hvip` is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode. Bits of @@ -643,7 +643,7 @@ When XLEN=32, `henvcfgh` is a of `henvcfg`. Register `henvcfgh` does not exist when XLEN=64. -==== Hypervisor Counter-Enable Register (`hcounteren`) +==== Hypervisor Counter-Enable (`hcounteren`) Register The counter-enable register `hcounteren` is a 32-bit register that controls the availability of the hardware performance monitoring @@ -665,7 +665,7 @@ readable unless the applicable bits are set in both `hcounteren` and read-only zero, indicating reads to the corresponding counter will cause an exception when V=1. Hence, they are effectively *WARL* fields. -==== Hypervisor Time Delta Register (`htimedelta`) +==== Hypervisor Time Delta (`htimedelta`) Register The `htimedelta` CSR is a 64-bit read/write register that contains the delta between the value of the `time` CSR and the value returned in VS-mode or @@ -685,7 +685,7 @@ When XLEN=32, `htimedeltah` is a 32-bit read/write register that aliases bits 63:32 of `htimedelta`. Register `htimedeltah` does not exist when XLEN=64. -==== Hypervisor Trap Value Register (`htval`) +==== Hypervisor Trap Value (`htval`) Register The `htval` register is an HSXLEN-bit read/write register formatted as shown in <>. When a trap is taken into @@ -746,7 +746,7 @@ software that writes a value to `htval` should read back from `htval` to confirm the stored value. ==== -==== Hypervisor Trap Instruction Register (`htinst`) +==== Hypervisor Trap Instruction (`htinst`) Register The `htinst` register is an HSXLEN-bit read/write register formatted as shown in <>. When a trap is taken into @@ -756,14 +756,14 @@ handling the trap. The values that may be written to `htinst` on a trap are documented in <>. [[htinstreg]] -.Hypervisor trap instruction register (`htinst`). +.Hypervisor trap instruction (`htinst`) register. include::images/bytefield/htinstreg.edn[] `htinst` is a *WARL* register that need only be able to hold the values that the implementation may automatically write to it on a trap. [[hgatp]] -==== Hypervisor Guest Address Translation and Protection Register (`hgatp`) +==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register The `hgatp` register is an HSXLEN-bit read/write register, formatted as shown in <> for HSXLEN=32 and @@ -883,7 +883,7 @@ modified, or if a VMID is reused, it may be necessary to execute an HFENCE.GVMA instruction (see <>) before or after writing `hgatp`. -==== Virtual Supervisor Status Register (`vsstatus`) +==== Virtual Supervisor Status (`vsstatus`) Register The `vsstatus` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `sstatus`, formatted as shown @@ -893,11 +893,11 @@ in <> when VSXLEN=32 and normally read or modify `sstatus` actually access `vsstatus` instead. [[vsstatusreg-rv32]] -.Virtual supervisor status register (`vstatus`) when VSXLEN=32. +.Virtual supervisor status (`vstatus`)register when VSXLEN=32. include::images/bytefield/vsstatusreg-rv32.edn[] [[vsstatusreg]] -.Virtual supervisor status register (`vsstatus`) when VSXLEN=64. +.Virtual supervisor status (`vsstatus`) register when VSXLEN=64. include::images/bytefield/vsstatusreg.edn[] The UXL field controls the effective XLEN for VU-mode, which may differ @@ -945,7 +945,7 @@ machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the MPRV feature in the `mstatus` register is used to execute a load or store _as though_ V=1. -==== Virtual Supervisor Interrupt Registers (`vsip` and `vsie`) +==== Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers The `vsip` and `vsie` registers are VSXLEN-bit read/write registers that are VS-mode’s versions of supervisor CSRs `sip` and `sie`, formatted as @@ -996,7 +996,7 @@ When bit 2 of `hideleg` is zero, `vsip`.SSIP and `vsie`.SSIE are read-only zeros. Else, `vsip`.SSIP and `vsie`.SSIE are aliases of `hip`.VSSIP and `hie`.VSSIE. -==== Virtual Supervisor Trap Vector Base Address Register (`vstvec`) +==== Virtual Supervisor Trap Vector Base Address (`vstvec`) Register The `vstvec` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `stvec`, formatted as shown in @@ -1009,7 +1009,7 @@ affect the behavior of the machine. .Virtual supervisor trap vector base address register `vstvec`. include::images/bytefield/vstvecreg.edn[] -==== Virtual Supervisor Scratch Register (`vsscratch`) +==== Virtual Supervisor Scratch (`vsscratch`) Register The `vsscratch` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `sscratch`, formatted as shown @@ -1022,7 +1022,7 @@ of `vsscratch` never directly affect the behavior of the machine. .Virtual supervisor scratch register `vsscratch`. include::images/bytefield/vsscratchreg.edn[] -==== Virtual Supervisor Exception Program Counter (`vsepc`) +==== Virtual Supervisor Exception Program Counter (`vsepc`) Register The `vsepc` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `sepc`, formatted as shown in @@ -1038,7 +1038,7 @@ that `sepc` can hold. .Virtual supervisor exception program counter (`vsepc`). include::images/bytefield/vsepcreg.edn[] -==== Virtual Supervisor Cause Register (`vscause`) +==== Virtual Supervisor Cause (`vscause`) Register The `vscause` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `scause`, formatted as shown in @@ -1054,7 +1054,7 @@ values that `scause` can hold. .Virtual supervisor cause register (`vscause`). include::images/bytefield/vscausereg.edn[] -==== Virtual Supervisor Trap Value Register (`vstval`) +==== Virtual Supervisor Trap Value (`vstval`) Register The `vstval` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `stval`, formatted as shown in @@ -1070,7 +1070,7 @@ that `stval` can hold. .Virtual supervisor trap value register (`vstval`). include::images/bytefield/vstvalreg.edn[] -==== Virtual Supervisor Address Translation and Protection Register (`vsatp`) +==== Virtual Supervisor Address Translation and Protection (`vsatp`) Register The `vsatp` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `satp`, formatted as shown in @@ -1082,11 +1082,11 @@ for guest virtual addresses (see <>). [[rv32vsatpreg]] -.Virtual supervisor address translation and protection register `vsatp` when VSXLEN=32. +.Virtual supervisor address translation and protection `vsatp` register when VSXLEN=32. include::images/bytefield/rv32vsatpreg.edn[] [[rv64vsatpreg]] -.Virtual supervisor address translation and protection register `vsatp` when VSXLEN=64. +.Virtual supervisor address translation and protection `vsatp` register when VSXLEN=64. include::images/bytefield/rv64vsatpreg.edn[] The `vsatp` register is considered _active_ for the purposes of the @@ -1290,7 +1290,7 @@ The hypervisor extension augments or modifies machine CSRs `mstatus`, `mstatush`, `mideleg`, `mip`, and `mie`, and adds CSRs `mtval2` and `mtinst`. -==== Machine Status Registers (`mstatus` and `mstatush`) +==== Machine Status (`mstatus` and `mstatush`) Registers The hypervisor extension adds two fields, MPV and GVA, to the machine-level `mstatus` or `mstatush` CSR, and modifies the behavior of @@ -1304,11 +1304,11 @@ to `mstatus` but to `mstatush`. MXLEN=32. [[hypervisor-mstatus]] -.Machine status register (`mstatus`) fpr RV64 when the hypervisor extension is implemented. +.Machine status (`mstatus`) register for RV64 when the hypervisor extension is implemented. include::images/bytefield/hypv-mstatus.edn[] [[hypervisor-mstatush]] -.Additional machine status register (`mstatush`) for RV32 when the hypervisor extension is implemented. The format of `mstatus` is unchanged for RV32. +.Additional machine status (`mstatush`) register for RV32 when the hypervisor extension is implemented. The format of `mstatus` is unchanged for RV32. include::images/bytefield/hypv-mstatush.edn[] The MPV bit (Machine Previous Virtualization Mode) is written by the @@ -1398,7 +1398,7 @@ always act as though V=1 and the nominal privilege mode were The `mstatus` register is a superset of the HS-level `sstatus` register but is not a superset of `vsstatus`. -==== Machine Interrupt Delegation Register (`mideleg`) +==== Machine Interrupt Delegation (`mideleg`) Register When the hypervisor extension is implemented, bits 10, 6, and 2 of `mideleg` (corresponding to the standard VS-level interrupts) are each @@ -1411,9 +1411,9 @@ past M-mode to HS-mode. For bits of `mideleg` that are zero, the corresponding bits in `hideleg`, `hip`, and `hie` are read-only zeros. -==== Machine Interrupt Registers (`mip` and `mie`) +==== Machine Interrupt (`mip` and `mie`) Registers -The hypervisor extension gives registers `mip` and `mie` additional +The hypervisor extension allows registers `mip` and `mie` additional active bits for the hypervisor-added interrupts. <> and <> show the standard portions (bits 15:0) of registers `mip` and `mie` when the hypervisor extension is implemented. @@ -1430,7 +1430,7 @@ Bits SGEIP, VSEIP, VSTIP, and VSSIP in `mip` are aliases for the same bits in hypervisor CSR `hip`, while SGEIE, VSEIE, VSTIE, and VSSIE in `mie` are aliases for the same bits in `hie`. -==== Machine Second Trap Value Register (`mtval2`) +==== Machine Second Trap Value (`mtval2`) Register The `mtval2` register is an MXLEN-bit read/write register formatted as shown in <>. When a trap is taken into @@ -1464,7 +1464,7 @@ the instruction as indicated by the virtual address in `mtval`. capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any. -==== Machine Trap Instruction Register (`mtinst`) +==== Machine Trap Instruction (`mtinst`) Register The `mtinst` register is an MXLEN-bit read/write register formatted as shown in <>. When a trap is taken into @@ -1474,7 +1474,7 @@ handling the trap. The values that may be written to `mtinst` on a trap are documented in <>. [[mtinstreg]] -.Machine trap instruction register (`mtinst`). +.Machine trap instruction (`mtinst`) register. include::images/bytefield/mtinstreg.edn[] `mtinst` is a *WARL* register that need only be able to hold the values that @@ -2175,7 +2175,7 @@ earlier. <<< [[tinst-values]] -.Values that may be automatically written to the trap instruction register (`mtinst` or `htinst`) on an exception trap. +.Values that may be automatically written to the trap instruction (`mtinst` or `htinst`) register on an exception trap. [float="center",align="center",cols="2,^,^,^,^",options="header"] |=== <.>|Exception From 7aeb6777d7b21e5d725089d11ad2c1e78a72ef71 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 21:36:46 -0500 Subject: [PATCH 06/20] Update v-st-ext.adoc Signed-off-by: Kersten Richter --- src/v-st-ext.adoc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc index 194e448e8..a77575581 100644 --- a/src/v-st-ext.adoc +++ b/src/v-st-ext.adoc @@ -145,7 +145,7 @@ otherwise, `mstatus.SD` is set in accordance with existing specifications. For implementations with a writable `misa.V` field, the `vsstatus.VS` field may exist even if `misa.V` is clear. -==== Vector type register, `vtype` +==== Vector type (`vtype`) Register The read-only XLEN-wide _vector_ _type_ CSR, `vtype` provides the default type used to interpret the contents of the vector register @@ -475,7 +475,7 @@ upon `vtype`. When the `vill` bit is set, the other XLEN-1 bits in `vtype` shall be zero. -==== Vector Length Register `vl` +==== Vector Length (`vl`) Register The _XLEN_-bit-wide read-only `vl` CSR can only be updated by the `vset{i}vl{i}` instructions, and the _fault-only-first_ vector load @@ -491,7 +491,7 @@ type. The smallest vector implementation with VLEN=32 and supporting SEW=8 would need at least six bits in `vl` to hold the values 0-32 (VLEN=32, with LMUL=8 and SEW=8, yields VLMAX=32). -==== Vector Byte Length `vlenb` +==== Vector Byte Length `vlenb` Register The _XLEN_-bit-wide read-only CSR `vlenb` holds the value VLEN/8, i.e., the vector register length in bytes. @@ -503,7 +503,7 @@ NOTE: Without this CSR, several instructions are needed to calculate VLEN in bytes, and the code has to disturb current `vl` and `vtype` settings which require them to be saved and restored. -==== Vector Start Index CSR `vstart` +==== Vector Start Index (`vstart`) Register The _XLEN_-bit-wide read-write `vstart` CSR specifies the index of the first element to be executed by a vector instruction, as described in @@ -569,7 +569,7 @@ next supported `vstart` element position. Alternatively, migration events can be constrained to only occur at mutually supported `vstart` locations. -==== Vector Fixed-Point Rounding Mode Register `vxrm` +==== Vector Fixed-Point Rounding Mode (`vxrm`) Register The vector fixed-point rounding-mode register holds a two-bit read-write rounding-mode field in the least-significant bits @@ -617,7 +617,7 @@ Bits `vxsat[XLEN-1:1]` should be written as zeros. The `vxsat` bit is mirrored in `vcsr`. -==== Vector Control and Status Register `vcsr` +==== Vector Control and Status (`vcsr`) Register The `vxrm` and `vxsat` separate CSRs can also be accessed via fields in the _XLEN_-bit-wide vector control and status CSR, `vcsr`. From aaa1bd9a3eab04b367e16c82750c96e4e4eae556 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 21:49:03 -0500 Subject: [PATCH 07/20] Update smcntrpmf.adoc Signed-off-by: Kersten Richter --- src/smcntrpmf.adoc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/smcntrpmf.adoc b/src/smcntrpmf.adoc index 339ced202..cc43b5180 100644 --- a/src/smcntrpmf.adoc +++ b/src/smcntrpmf.adoc @@ -14,7 +14,7 @@ This proposal remedies these issues by introducing privilege mode filtering for [[csrs]] === CSRs -==== Machine Counter Configuration Registers (mcyclecfg, minstretcfg) +==== Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode filtering for the cycle and instret counters, respectively. @@ -70,4 +70,4 @@ For the instret counter, most instructions do not affect mode transitions, so fo The instret definition above is intended to ensure that the counter increments in a predictable fashion. For example, consider a scenario where minstretcfg is configured such that all modes other than U-mode are inhibited. A user mode load should increment only once, even if it takes a page fault or other exception. With this definition, the faulting execution of the load will not increment (it does not retire), the handler instructions will not increment (they execute in an inhibited mode), including the xRET (it arguably retires in a non-inhibited mode, but it originates in an inhibited mode). Only once the load is re-executed and retires will it increment instret. In cases where an instruction is emulated by software running in a privilege mode that is inhibited in minstretcfg, the emulation routine must emulate the instret increment. -==== \ No newline at end of file +==== From 8816a0d9f861b7678557247baafe0d4499c607c6 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 21:50:34 -0500 Subject: [PATCH 08/20] Update smcdeleg.adoc Signed-off-by: Kersten Richter --- src/smcdeleg.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/smcdeleg.adoc b/src/smcdeleg.adoc index fd67d8225..9fae18dcb 100644 --- a/src/smcdeleg.adoc +++ b/src/smcdeleg.adoc @@ -115,7 +115,7 @@ Smcntrpmf is implemented, `sireg2` and `sireg5` provide access only to a subset of the counter configuration registers. Counter configuration register bit 62 (MINH) is read-only 0 when accessed through `sireg*`. -=== Supervisor Counter Inhibit Register (`scountinhibit`) +=== Supervisor Counter Inhibit (`scountinhibit`) Register Smcdeleg/Ssccfg defines a new `scountinhibit` register, a masked alias of `mcountinhibit`. For counters delegated to S-mode, the associated From 86c03804e1536eca64c355bcee7bd53f26e01fae Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 22:02:16 -0500 Subject: [PATCH 09/20] Update sstc.adoc Signed-off-by: Kersten Richter --- src/sstc.adoc | 102 +++++++++++++++++++++++++------------------------- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/src/sstc.adoc b/src/sstc.adoc index 5c72adaca..fe8d8f679 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -27,15 +27,15 @@ and the VS-level vstimecmp CSR. === Machine and Supervisor Level Additions -==== Supervisor Timer (stimecmp) Register +==== Supervisor Timer (`stimecmp`) Register This extension adds this new CSR. -The stimecmp CSR is a 64-bit register and has 64-bit precision on all RV32 and -RV64 systems. In RV32 only, accesses to the stimecmp CSR access the low 32 -bits, while accesses to the stimecmph CSR access the high 32 bits of stimecmp. +The `stimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and +RV64 systems. In RV32 only, accesses to the `stimecmp` CSR access the low 32 +bits, while accesses to the `stimecmph` CSR access the high 32 bits of `stimecmp`. -The CSR numbers for stimecmp / stimecmph are 0x14D / 0x15D (within the +The CSR numbers for `stimecmp` / `stimecmph` are 0x14D / 0x15D (within the Supervisor Trap Setup block of CSRs). A supervisor timer interrupt becomes pending - as reflected in the STIP bit in @@ -49,7 +49,7 @@ based on the standard interrupt enable and delegation rules. [NOTE] ==== A spurious timer interrupt might occur if an interrupt handler advances -stimecmp then immediately returns, because STIP might not yet have fallen in +`stimecmp` then immediately returns, because STIP might not yet have fallen in the interim. All software should be written to assume this event is possible, but most software should assume this event is extremely unlikely. It is almost always more performant to incur an occasional spurious timer interrupt than to @@ -66,7 +66,7 @@ existing S-mode software that uses this SEE facility, while new S-mode software takes advantage of stimecmp directly.) ==== -==== Machine Interrupt (mip and mie) Registers +==== Machine Interrupt (`mip` and `mie`) Registers This extension modifies the description of the STIP/STIE bits in these registers as follows: @@ -75,60 +75,60 @@ If supervisor mode is implemented, its mip.STIP and mie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If the stimecmp register is not implemented, STIP is writable in mip, and may be written by M-mode software to deliver timer interrupts to -S-mode. If the stimecmp (supervisor-mode timer compare) register is +S-mode. If the `stimecmp` (supervisor-mode timer compare) register is implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp. This timer interrupt signal is -cleared by writing stimecmp with a value greater than the current time value. +cleared by writing `stimecmp` with a value greater than the current time value. -==== Supervisor Interrupt (sip and sie) Registers +==== Supervisor Interrupt (`sip` and `sie`) Registers This extension modifies the description of the STIP/STIE bits in these registers as follows: -Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits +Bits `sip.STIP` and `sie.STIE` are the interrupt-pending and interrupt-enable bits for supervisor level timer interrupts. If implemented, STIP is read-only in -sip, and is either set and cleared by the execution environment (if stimecmp is +sip, and is either set and cleared by the execution environment (if `stimecmp` is not implemented), or reflects the timer interrupt signal resulting from -stimecmp (if stimecmp is implemented). The sip.STIP bit, in response to timer -interrupts generated by stimecmp, is set and cleared by writing stimecmp with a +`stimecmp` (if `stimecmp` is implemented). The sip.STIP bit, in response to timer +interrupts generated by `stimecmp`, is set and cleared by writing `stimecmp` with a value that respectively is less than or equal to, or greater than, the current time value. -==== Machine Counter-Enable (mcounteren) Register +==== Machine Counter-Enable (`mcounteren`) Register This extension adds to the description of the TM bit in this register as follows: In addition, when the TM bit in the mcounteren register is clear, attempts to -access the stimecmp or vstimecmp register while executing in a mode less +access the `stimecmp` or `vstimecmp` register while executing in a mode less privileged than M will cause an illegal instruction exception. When this bit -is set, access to the stimecmp or vstimecmp register is permitted in S-mode if -implemented, and access to the vstimecmp register (via stimecmp) is permitted +is set, access to the `stimecmp` or `vstimecmp` register is permitted in S-mode if +implemented, and access to the `vstimecmp` register (via `stimecmp`) is permitted in VS-mode if implemented and not otherwise prevented by the TM bit in -hcounteren. +`hcounteren`. === Hypervisor Extension Additions -==== Virtual Supervisor Timer (vstimecmp) Register +==== Virtual Supervisor Timer (`vstimecmp`) Register This extension adds this new CSR. -The vstimecmp CSR is a 64-bit register and has 64-bit precision on all RV32 and -RV64 systems. In RV32 only, accesses to the vstimecmp CSR access the low 32 -bits, while accesses to the vstimecmph CSR access the high 32 bits of +The `vstimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and +RV64 systems. In RV32 only, accesses to the `vstimecmp` CSR access the low 32 +bits, while accesses to the `vstimecmph` CSR access the high 32 bits of vstimecmp. -The proposed CSR numbers for vstimecmp / vstimecmph are 0x24D / 0x25D (within +The proposed CSR numbers for `vstimecmp` / `vstimecmph` are 0x24D / 0x25D (within the Virtual Supervisor Registers block of CSRs, and mirroring the CSR numbers for stimecmp/stimecmph). A virtual supervisor timer interrupt becomes pending - as reflected in the -VSTIP bit in the hip register - whenever (time + htimedelta), truncated to 64 -bits, contains a value greater than or equal to vstimecmp, treating the values -as unsigned integers. Writes to vstimecmp and htimedelta are guaranteed to be +VSTIP bit in the `hip` register - whenever (`time` + `htimedelta`), truncated to 64 +bits, contains a value greater than or equal to `vstimecmp`, treating the values +as unsigned integers. Writes to `vstimecmp` and `htimedelta` are guaranteed to be reflected in VSTIP eventually, but not necessarily immediately. The interrupt -remains posted until vstimecmp becomes greater than (time + htimedelta) - -typically as a result of writing vstimecmp. The interrupt will be taken based +remains posted until `vstimecmp` becomes greater than (`time` + `htimedelta`) - +typically as a result of writing `vstimecmp`. The interrupt will be taken based on the standard interrupt enable and delegation rules while V=1. [NOTE] @@ -141,7 +141,7 @@ ensures compatibility with existing guest VS-mode software that uses this SEE facility, while new VS-mode software takes advantage of vstimecmp directly.) ==== -==== Hypervisor Interrupt (hvip, hip, and hie) Registers +==== Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers This extension modifies the description of the VSTIP/VSTIE bits in the hip/hie registers as follows: @@ -149,39 +149,39 @@ registers as follows: Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enable bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and the timer interrupt signal resulting from -vstimecmp (if vstimecmp is implemented). The hip.VSTIP bit, in response to -timer interrupts generated by vstimecmp, is set and cleared by writing -vstimecmp with a value that respectively is less than or equal to, or greater -than, the current (time + htimedelta) value. The hip.VSTIP bit remains defined +vstimecmp (if `vstimecmp` is implemented). The hip.VSTIP bit, in response to +timer interrupts generated by `vstimecmp`, is set and cleared by writing +`vstimecmp` with a value that respectively is less than or equal to, or greater +than, the current (`time` + `htimedelta`) value. The hip.VSTIP bit remains defined while V=0 as well as V=1. -==== Hypervisor Counter-Enable (hcounteren) Register +==== Hypervisor Counter-Enable (`hcounteren`) Register This extension adds to the description of the TM bit in this register as follows: -In addition, when the TM bit in the hcounteren register is clear, attempts to -access the vstimecmp register (via stimecmp) while executing in VS-mode will -cause a virtual instruction exception if the same bit in mcounteren is set. -When this bit and the same bit in mcounteren are both set, access to the -vstimecmp register (if implemented) is permitted in VS-mode. +In addition, when the TM bit in the `hcounteren` register is clear, attempts to +access the `vstimecmp` register (via stimecmp) while executing in VS-mode will +cause a virtual instruction exception if the same bit in `mcounteren` is set. +When this bit and the same bit in `mcounteren` are both set, access to the +`vstimecmp` register (if implemented) is permitted in VS-mode. -=== Environment Config (menvcfg/henvcfg) Support +=== Environment Config (`menvcfg` or `henvcfg`) Support -Enable/disable bits for this extension are provided in the new menvcfg / -henvcfg CSRs. +Enable/disable bits for this extension are provided in the new `menvcfg` / +`henvcfg` CSRs. -Bit 63 of menvcfg (or bit 31 of menvcfgh) - named STCE (STimecmp Enable) - -enables stimecmp for S-mode when set to one, and the same bit of henvcfg -enables vstimecmp for VS-mode. These STCE bits are WARL and are hard-wired to 0 +Bit 63 of `menvcfg` (or bit 31 of `menvcfgh`) - named STCE (STimecmp Enable) - +enables `stimecmp` for S-mode when set to one, and the same bit of henvcfg +enables `vstimecmp` for VS-mode. These STCE bits are WARL and are hard-wired to 0 when this extension is not implemented. -When this extension is implemented and STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a -mode other than M-mode raises an illegal instruction exception, STCE in henvcfg -is read-only zero, and STIP in mip and sip reverts to its defined behavior as +When this extension is implemented and STCE in `menvcfg` is zero, an attempt to access `stimecmp` or `vstimecmp` in a +mode other than M-mode raises an illegal instruction exception, STCE in `henvcfg` +is read-only zero, and STIP in `mip` and `sip` reverts to its defined behavior as if this extension is not implemented. Further, if the H extension is implemented, then hip.VSTIP also reverts its defined behavior as if this extension is not implemented. -But when STCE in menvcfg is one and STCE in henvcfg is zero, an attempt to access -stimecmp (really vstimecmp) when V = 1 raises a virtual instruction exception, +But when STCE in `menvcfg` is one and STCE in `henvcfg` is zero, an attempt to access +`stimecmp` (really `vstimecmp`) when V = 1 raises a virtual instruction exception, and VSTIP in hip reverts to its defined behavior as if this extension is not implemented. From 86cd0d12ed6186a62aa7393f3d8305d3ed9816a6 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:16:26 -0500 Subject: [PATCH 10/20] Update src/hypervisor.adoc Signed-off-by: Kersten Richter --- src/hypervisor.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 09d70a2b4..6bd8a98f4 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -893,7 +893,7 @@ in <> when VSXLEN=32 and normally read or modify `sstatus` actually access `vsstatus` instead. [[vsstatusreg-rv32]] -.Virtual supervisor status (`vstatus`)register when VSXLEN=32. +.Virtual supervisor status (`vstatus`) register when VSXLEN=32. include::images/bytefield/vsstatusreg-rv32.edn[] [[vsstatusreg]] From ccc3d194faab5569e926720f4bf22a46f41580b3 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:16:56 -0500 Subject: [PATCH 11/20] Update src/hypervisor.adoc Signed-off-by: Kersten Richter --- src/hypervisor.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 6bd8a98f4..bafdf1ac2 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -1413,7 +1413,7 @@ For bits of `mideleg` that are zero, the corresponding bits in ==== Machine Interrupt (`mip` and `mie`) Registers -The hypervisor extension allows registers `mip` and `mie` additional +The hypervisor extension gives registers `mip` and `mie` additional active bits for the hypervisor-added interrupts. <> and <> show the standard portions (bits 15:0) of registers `mip` and `mie` when the hypervisor extension is implemented. From e825d9f423d16a0dd997c89883004319ec704af2 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:17:57 -0500 Subject: [PATCH 12/20] Update src/sscofpmf.adoc Signed-off-by: Kersten Richter --- src/sscofpmf.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc index 4d301d579..58f1bdebd 100644 --- a/src/sscofpmf.adoc +++ b/src/sscofpmf.adoc @@ -101,7 +101,7 @@ maintaining a bit mask reflecting which counters are active and due to eventually overflow. ==== -=== Supervisor Count Overflow (scountovf) Register +=== Supervisor Count Overflow (`scountovf`) Register This extension adds the `scountovf` CSR, a 32-bit read-only register that contains shadow copies of From b0a6a3886bd003a5686243871fa936613390445e Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:19:16 -0500 Subject: [PATCH 13/20] Update src/sstc.adoc Signed-off-by: Kersten Richter --- src/sstc.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sstc.adoc b/src/sstc.adoc index fe8d8f679..5efcd0112 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -85,7 +85,7 @@ cleared by writing `stimecmp` with a value greater than the current time value. This extension modifies the description of the STIP/STIE bits in these registers as follows: -Bits `sip.STIP` and `sie.STIE` are the interrupt-pending and interrupt-enable bits +Bits `sip`.STIP and `sie`.STIE are the interrupt-pending and interrupt-enable bits for supervisor level timer interrupts. If implemented, STIP is read-only in sip, and is either set and cleared by the execution environment (if `stimecmp` is not implemented), or reflects the timer interrupt signal resulting from From 622ccc5812e6686db5604a271046f2349ba84eeb Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:20:14 -0500 Subject: [PATCH 14/20] Update src/sstc.adoc Signed-off-by: Kersten Richter --- src/sstc.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sstc.adoc b/src/sstc.adoc index 5efcd0112..4421b2212 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -89,7 +89,7 @@ Bits `sip`.STIP and `sie`.STIE are the interrupt-pending and interrupt-enable bi for supervisor level timer interrupts. If implemented, STIP is read-only in sip, and is either set and cleared by the execution environment (if `stimecmp` is not implemented), or reflects the timer interrupt signal resulting from -`stimecmp` (if `stimecmp` is implemented). The sip.STIP bit, in response to timer +`stimecmp` (if `stimecmp` is implemented). The `sip`.STIP bit, in response to timer interrupts generated by `stimecmp`, is set and cleared by writing `stimecmp` with a value that respectively is less than or equal to, or greater than, the current time value. From be4662576c82c47ec4334221e1d2d195e9061af1 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:21:06 -0500 Subject: [PATCH 15/20] Update src/v-st-ext.adoc Signed-off-by: Kersten Richter --- src/v-st-ext.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc index a77575581..5b090a0a7 100644 --- a/src/v-st-ext.adoc +++ b/src/v-st-ext.adoc @@ -491,7 +491,7 @@ type. The smallest vector implementation with VLEN=32 and supporting SEW=8 would need at least six bits in `vl` to hold the values 0-32 (VLEN=32, with LMUL=8 and SEW=8, yields VLMAX=32). -==== Vector Byte Length `vlenb` Register +==== Vector Byte Length (`vlenb`) Register The _XLEN_-bit-wide read-only CSR `vlenb` holds the value VLEN/8, i.e., the vector register length in bytes. From aa4a25cf6831cc962dbc72587a1804aaf8290aae Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:22:23 -0500 Subject: [PATCH 16/20] Update src/supervisor.adoc Signed-off-by: Kersten Richter --- src/supervisor.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/supervisor.adoc b/src/supervisor.adoc index e87fbdd7d..5b93c53f0 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -176,7 +176,7 @@ of one endianness to execute user-mode programs of the opposite endianness. ==== -==== Supervisor Trap Vector Base Address(`stvec`) Register +==== Supervisor Trap Vector Base Address (`stvec`) Register The `stvec` register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a From c0091849d8ba44b87d8230af53b21284b7196f9d Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:24:58 -0500 Subject: [PATCH 17/20] Update src/sstc.adoc Signed-off-by: Kersten Richter --- src/sstc.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sstc.adoc b/src/sstc.adoc index 4421b2212..316324374 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -149,7 +149,7 @@ registers as follows: Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enable bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and the timer interrupt signal resulting from -vstimecmp (if `vstimecmp` is implemented). The hip.VSTIP bit, in response to +`vstimecmp` (if `vstimecmp` is implemented). The `hip`.VSTIP bit, in response to timer interrupts generated by `vstimecmp`, is set and cleared by writing `vstimecmp` with a value that respectively is less than or equal to, or greater than, the current (`time` + `htimedelta`) value. The hip.VSTIP bit remains defined From f35e5465029a4db2ad8591fbe8a585e1be422054 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:25:35 -0500 Subject: [PATCH 18/20] Update src/sstc.adoc Signed-off-by: Kersten Richter --- src/sstc.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sstc.adoc b/src/sstc.adoc index 316324374..fa6ff8bf0 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -152,7 +152,7 @@ logical-OR of hvip.VSTIP and the timer interrupt signal resulting from `vstimecmp` (if `vstimecmp` is implemented). The `hip`.VSTIP bit, in response to timer interrupts generated by `vstimecmp`, is set and cleared by writing `vstimecmp` with a value that respectively is less than or equal to, or greater -than, the current (`time` + `htimedelta`) value. The hip.VSTIP bit remains defined +than, the current (`time` + `htimedelta`) value. The `hip`.VSTIP bit remains defined while V=0 as well as V=1. ==== Hypervisor Counter-Enable (`hcounteren`) Register From 56f1708b4805c07d38c632604e2045c5a3da574f Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:26:07 -0500 Subject: [PATCH 19/20] Update src/v-st-ext.adoc Signed-off-by: Kersten Richter --- src/v-st-ext.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc index 5b090a0a7..629471991 100644 --- a/src/v-st-ext.adoc +++ b/src/v-st-ext.adoc @@ -145,7 +145,7 @@ otherwise, `mstatus.SD` is set in accordance with existing specifications. For implementations with a writable `misa.V` field, the `vsstatus.VS` field may exist even if `misa.V` is clear. -==== Vector type (`vtype`) Register +==== Vector Type (`vtype`) Register The read-only XLEN-wide _vector_ _type_ CSR, `vtype` provides the default type used to interpret the contents of the vector register From 8ebfb357357c2119581225e95e25908b393305e6 Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Thu, 18 Apr 2024 07:27:14 -0500 Subject: [PATCH 20/20] Update src/sstc.adoc Signed-off-by: Kersten Richter --- src/sstc.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sstc.adoc b/src/sstc.adoc index fa6ff8bf0..3b4a9b84e 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -166,7 +166,7 @@ cause a virtual instruction exception if the same bit in `mcounteren` is set. When this bit and the same bit in `mcounteren` are both set, access to the `vstimecmp` register (if implemented) is permitted in VS-mode. -=== Environment Config (`menvcfg` or `henvcfg`) Support +=== Environment Config (`menvcfg` and `henvcfg`) Support Enable/disable bits for this extension are provided in the new `menvcfg` / `henvcfg` CSRs.