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Introduce IALIGN; propose misa.C semantics #139

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merged 3 commits into from Mar 3, 2018

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commented Feb 22, 2018

This is still being debated; I'm making the PR so the PrivArch group can discuss something concrete.

@aswaterman aswaterman requested a review from kasanovic Feb 22, 2018

When clearing the ``C'' bit in {\tt misa}, software must ensure that the
current {\tt pc} is 4-byte aligned and that all {\em x}{\tt epc} registers
contain 4-byte-aligned values.
Writing {\tt misa} may reduce IALIGN, e.g., by disabling the ``C''

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sorear Feb 22, 2018

s/reduce/increase/

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aswaterman Feb 22, 2018

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thanks

@aswaterman aswaterman force-pushed the misa-c branch from e5cfeab to a4ade78 Feb 22, 2018

aswaterman added a commit to riscv/riscv-isa-sim that referenced this pull request Feb 22, 2018

Implement clearing-misa.C-while-PC-is-misaligned proposal
See riscv/riscv-isa-manual#139

Not adopted yet, but I'm putting the implementation here for reference.

aswaterman added a commit to riscv/riscv-tests that referenced this pull request Feb 22, 2018

aswaterman added a commit to riscv/riscv-tests that referenced this pull request Feb 27, 2018

@aswaterman aswaterman merged commit 5f8294b into master Mar 3, 2018

aswaterman added a commit to riscv/riscv-isa-sim that referenced this pull request Mar 3, 2018

Implement clearing-misa.C-while-PC-is-misaligned proposal
See riscv/riscv-isa-manual#139

Not adopted yet, but I'm putting the implementation here for reference.

@aswaterman aswaterman deleted the misa-c branch Mar 3, 2018

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