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diff --git a/ChangeLog.md b/ChangeLog.md
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+riscvOVPsim Fixed Platform Kit Change Log
+===
+
+# Changes since last release
+
+- Added ChangeLog.md to track changes
+
+# Changes for v20180607
+
+- initial release
+
+---
+
+This is the riscvOVPsim/Changelog.md  
diff --git a/LICENSE.pdf b/LICENSE.pdf
diff --git a/README.md b/README.md
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+riscvOVPsim
+===
+A Complete, Fully Functional, Configurable RISC-V Simulator
+===
+
+Author: Imperas Software, Ltd., using OVP Open Standard APIs  
+Date   : 12 Jun 2018 
+Version: 20180612.0  
+License: Model source included under Apache 2.0 open source license  
+License: Simulator riscvOVPsim licensed under Open Virtual Platforms (OVP) Fixed Platform Kits license  
+RISC-V Specifications currently supported:
+- RISCV.org User 2.2, 2.3a (draft)  
+- RISCV.org Privilege 1.10, 1.11a (draft)[not hypervisors as currently in flux]
+
+About riscvOVPsim
+---
+The **riscvOVPsim** simulator implements the full and complete functionality of the RISC-V Foundation's public User and Privilege specifications.  
+
+The simulator is command line configurable to enable/disable all current optional and processor specific options. 
+
+The simulator is developed, licensed and maintained by [Imperas Software](http://www.imperas.com/riscv) and it is fully compliant to the OVP open standard APIs. 
+
+As a member of the RISC-V Foundation community of software and hardware innovators collaboratively driving RISC-V adoption, Imperas has developed the riscvOVPsim simulator to assist RISC-V adopters to become compliant to the RISC-V specifications. The latest RISC-V compliance test suite and framework can be downloaded from https://www.github.com/riscv/riscv-compliance . 
+
+riscvOVPsim includes an industrial quality model and simulator of RISC-V processors for use for compliance and test development. It has been developed for personal, academic, or commercial use, and the model is provided as open source.
+
+Runtime configurable settings for all RISC-V specification options makes it very easy to compare run time results with any RTL implementations.
+
+Full commercial features including variant selection, comprehensive trace, GDB/Eclipse graphical source code debug, semihosting, and RISC-V foundation signature dump facility for compliance testing.
+
+More information: [riscvOVPsim user guide](doc/riscvOVPsim_User_Guide.pdf)  
+Model Source: [source](source)  
+Examples: [examples](examples)  
+
+![](riscvOVPsim.jpg)  
+riscvOVPsim is a fixed function simulation of one configurable processor model in a fixed platform. Full extendable platform simulations of reference designs booting etc FreeRTOS, Linux, SMP Linux etc. are available as open source and are available from [www.IMPERAS.com](http://www.imperas.com), [www.OVPworld.org](http://www.OVPworld.org).  
+
+
+Debugging using GDB / Eclipse
+---
+The same fixed platform can be used to debug the application using GDB and Eclipse.
+
+For GDB debug add the command line argument _-gdbconsole_, this will start the GDB debugger and connect to the virtual platform.
+
+For Eclipse debug, using CDT, a configuration to attach to an external remote application for debug should be made. The port to attach to is opened on the running virtual platform by adding the command line argument _-port <port number>_ when starting the virtual platform. 
+
+Please see the [riscvOVPsim user guide](doc/riscvOVPsim_User_Guide.pdf) for full details.
+
+Using riscvOVPsim
+---
+To use the simulator, just download the files, go into one of the example directories, and execute the provided run scripts.
+For example on Linux:  
+
+> $ cd examples  
+> $ cd fibonacci  
+> $ RUN_RV32_fibonacci.sh  
+> 
+> CpuManagerFixedPlatform (64-Bit) 20180425.0 Open Virtual Platform simulator from [www.IMPERAS.com](http://www.imperas.com).  
+> Copyright (c) 2005-2018 Imperas Software Ltd.  Contains Imperas Proprietary Information.  
+> Licensed Software, All Rights Reserved.  
+> Visit [www.IMPERAS.com](http://www.imperas.com) for multicore debug, verification and analysis solutions.  
+>   
+> CpuManagerFixedPlatform started: Tue Apr 24 19:12:06 2018  
+>   
+> Info (OR_OF) Target 'riscvOVPsim/cpu' has object file read from 'fibonacci.RISCV32-O0-g.elf'  
+> Info (OR_PH) Program Headers:  
+> Info (OR_PH) Type           Offset     VirtAddr   PhysAddr   FileSiz    MemSiz     Flags Align  
+> Info (OR_PD) LOAD           0x00000000 0x00010000 0x00010000 0x00016998 0x00016998 R-E   1000  
+> Info (OR_PD) LOAD           0x00017000 0x00027000 0x00027000 0x000009c0 0x00000a54 RW-   1000  
+> starting fib(38)...  
+> fib(0) = 0  
+> fib(1) = 1  
+> fib(2) = 1  
+> fib(3) = 2  
+> ...  
+> fib(36) = 14930352  
+> fib(37) = 24157817  
+> finishing...  
+> Info   
+> Info ---------------------------------------------------  
+> Info CPU 'riscvOVPsim/cpu' STATISTICS  
+> Info   Type                  : riscv (RV32IMAC)  
+> Info   Nominal MIPS          : 100  
+> Info   Final program counter : 0x100ac  
+> Info   Simulated instructions: 4,400,537,204  
+> Info   Simulated MIPS        : 1439.2  
+> Info ---------------------------------------------------  
+> Info   
+> Info ---------------------------------------------------  
+> Info SIMULATION TIME STATISTICS  
+> Info   Simulated time        : 44.01 seconds  
+> Info   User time             : 3.06 seconds  
+> Info   System time           : 0.00 seconds  
+> Info   Elapsed time          : 3.10 seconds  
+> Info   Real time ratio       : 14.18x faster  
+> Info ---------------------------------------------------  
+>   
+> CpuManagerFixedPlatform finished: Tue Apr 24 19:12:10 2018  
+>   
+> CpuManagerFixedPlatform (64-Bit) 20180425.0 Open Virtual Platform simulator from [www.IMPERAS.com](http://www.imperas.com).  
+> Visit [www.IMPERAS.com](http://www.imperas.com) for multicore debug, verification and analysis solutions.  
+  
+Extending riscvOVPsim and building your own models and platforms
+---
+riscvOVPsim is a fixed function simulation of one configurable processor model in a fixed platform. Full extendable platform simulations of reference designs booting etc FreeRTOS, Linux, SMP Linux etc. are available as open source and are available from [www.IMPERAS.com](http://www.imperas.com), [www.OVPworld.org](http://www.OVPworld.org).  
+
+
+About Open Virtual Platforms (OVP) and Imperas Software
+---
+**Open Virtual Platforms** was created in 2008 to provide an open standard set of APIs and methodology to develop virtual platforms and simulation technology. 
+[www.OVPworld.org](http://www.OVPworld.org/riscv).
+
+**Imperas Software Ltd.** is the leading independent commercial developer of virtual platforms and high-performance software simulation solutions for embedded processor and systems. Leading semiconductor and embedded software companies use Imperas simulators for their processor based simulation solutions.
+[www.imperas.com](http://www.imperas.com/riscv).
+
+![OVP Image ](http://www.imperas.com/sites/default/files/partner-logos/ovp_0.jpg)  
+![Imperas Imperas](http://www.imperas.com/sites/all/themes/tophit/logo.png)  
+---
+
+
+This is the riscvOVPsim/README.md  
diff --git a/bin/Linux64/libdwarf-20120410.so b/bin/Linux64/libdwarf-20120410.so
diff --git a/bin/Linux64/libelf.so.0.8.13 b/bin/Linux64/libelf.so.0.8.13
diff --git a/bin/Linux64/libtcl8.4.so b/bin/Linux64/libtcl8.4.so
diff --git a/bin/Linux64/riscv64-unknown-elf-gdb b/bin/Linux64/riscv64-unknown-elf-gdb
diff --git a/bin/Linux64/riscvOVPsim.exe b/bin/Linux64/riscvOVPsim.exe
diff --git a/bin/README.md b/bin/README.md
@@ -0,0 +1,5 @@
+riscvOVPsim/bin/README.md
+---
+In this directory are the different host platforms that the simulator runs on.
+
+Each directory includes the binary libraries and executables required to run the simulation.
diff --git a/bin/Windows64/libdwarf-20120410.dll b/bin/Windows64/libdwarf-20120410.dll
diff --git a/bin/Windows64/libelf-0.8.13.dll b/bin/Windows64/libelf-0.8.13.dll
diff --git a/bin/Windows64/lmgr11_imperas.dll b/bin/Windows64/lmgr11_imperas.dll
diff --git a/bin/Windows64/pthreadGC2-w64.dll b/bin/Windows64/pthreadGC2-w64.dll
diff --git a/bin/Windows64/riscv64-unknown-elf-gdb.exe b/bin/Windows64/riscv64-unknown-elf-gdb.exe
diff --git a/bin/Windows64/riscvOVPsim.exe b/bin/Windows64/riscvOVPsim.exe
diff --git a/bin/Windows64/tcl85.dll b/bin/Windows64/tcl85.dll
diff --git a/doc/README.md b/doc/README.md
@@ -0,0 +1,9 @@
+riscvOVPsim/doc/README.md
+---
+In this directory is the simulator documentation as a pdf file.
+
+The document lists the different processor variants and configurations the simulator supports and explains all the different command line options needed to execute cross compiled RISC-V target _elf_ files.
+
+To see all the RISC-V models available from OVP visit [risc-v-processors](http://www.ovpworld.org/library/wikka.php?wakka=RiscVprocessors).
+
+To see all the detailed documentation of the models visit [risc-v-processors pdf documents](http://www.ovpworld.org/procmodeldocs) (and scroll down to the section on RISC-V).
diff --git a/doc/riscvOVPsim_User_Guide.pdf b/doc/riscvOVPsim_User_Guide.pdf
diff --git a/examples/CoreMark/32_core_portme.c b/examples/CoreMark/32_core_portme.c
@@ -0,0 +1,146 @@
+/* 
+	File : core_portme.c
+*/
+/*
+	Author : Shay Gal-On, EEMBC
+	Legal : TODO!
+*/ 
+#include <stdio.h>
+#include <stdlib.h>
+#include "coremark.h"
+#include "simulatorIntercepts.h"
+
+#if VALIDATION_RUN
+	volatile ee_s32 seed1_volatile=0x3415;
+	volatile ee_s32 seed2_volatile=0x3415;
+	volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+	volatile ee_s32 seed1_volatile=0x0;
+	volatile ee_s32 seed2_volatile=0x0;
+	volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+	volatile ee_s32 seed1_volatile=0x8;
+	volatile ee_s32 seed2_volatile=0x8;
+	volatile ee_s32 seed3_volatile=0x8;
+#endif
+	volatile ee_s32 seed4_volatile=ITERATIONS;
+	volatile ee_s32 seed5_volatile=0;
+/* Porting : Timing functions
+	How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+	e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. 
+	Sample implementation for standard time.h and windows.h definitions included.
+*/
+/* Define : TIMER_RES_DIVIDER
+	Divider to trade off timer resolution and total time that can be measured.
+
+	Use lower values to increase resolution, but make sure that overflow does not occur.
+	If there are issues with the return value overflowing, increase this value.
+	*/
+
+// All processors will run at default 100MIPS
+#ifdef CLOCKS_PER_SEC
+#undef CLOCKS_PER_SEC
+#endif
+#define CLOCKS_PER_SEC 100000000
+
+#define NSECS_PER_SEC CLOCKS_PER_SEC
+#define CORETIMETYPE clock_t
+//#define GETMYTIME(_t) (*_t=clock())
+//#define CORETIMETYPE ee_u32
+
+//Using Imperas Intercepts
+//#define GETMYTIME(_t) (*_t=impProcessorInstructionCount())
+
+// Using mcycle register
+#define read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+#define GETMYTIME(_t) (*_t=read_csr(mcycle))
+
+
+#define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+#define TIMER_RES_DIVIDER 1
+#define SAMPLE_TIME_IMPLEMENTATION 1
+#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER)
+
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function : start_time
+	This function will be called right before starting the timed portion of the benchmark.
+
+	Implementation may be capturing a system timer (as implemented in the example code) 
+	or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+	GETMYTIME(&start_time_val );
+}
+/* Function : stop_time
+	This function will be called right after ending the timed portion of the benchmark.
+
+	Implementation may be capturing a system timer (as implemented in the example code) 
+	or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+	GETMYTIME(&stop_time_val );
+}
+/* Function : get_time
+	Return an abstract "ticks" number that signifies time on the system.
+	
+	Actual value returned may be cpu cycles, milliseconds or any other value,
+	as long as it can be converted to seconds by <time_in_secs>.
+	This methodology is taken to accomodate any hardware or simulated platform.
+	The sample implementation returns millisecs by default, 
+	and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+	CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+	return elapsed;
+}
+/* Function : time_in_secs
+	Convert the value returned by get_time to seconds.
+
+	The <secs_ret> type is used to accomodate systems with no support for floating point.
+	Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+	secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+	return retval;
+}
+
+ee_u32 default_num_contexts=1;
+
+/* Function : portable_init
+	Target specific initialization code 
+	Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+	if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+		ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
+	}
+	if (sizeof(ee_u32) != 4) {
+		ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+	}
+	p->portable_id=1;
+}
+/* Function : portable_fini
+	Target specific final code 
+*/
+void portable_fini(core_portable *p)
+{
+	p->portable_id=0;
+}
+
+#if (MEM_METHOD==MEM_MALLOC)
+
+void *portable_malloc(size_t size) {
+    return malloc(size);
+}
+
+void portable_free(void *p) {
+    free(p);
+}
+#endif