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Add draft Zvfh and Zvfhmin specs #780
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Vector instructions that process IEEE 754 binary16 numbers were included in draft versions of the vector extension, but they were separated from the V extension prior to ratification. This PR adds them back. The Zvfh extension adds IEEE 754 binary16 support to all FP instructions. The Zvfhmin extension adds only the conversions to and from binary32.
nick-knight
approved these changes
Mar 11, 2022
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| When the Zvfh extension is implemented, all instructions in Sections | ||
| <<sec-vector-float>>, <<sec-vector-float-reduce>>, | ||
| <<sec-vector-float-reduce-widen>>, <<sec-vector-float-move>>, | ||
| <<sec-vfslide1up>>, and <<sec-vfslide1down>> | ||
| become defined when SEW=16. | ||
| The EEW=16 floating-point operands of these instructions use the binary16 | ||
| format. | ||
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| Additionally, conversions between 8-bit integers and binary16 values are | ||
| provided. The floating-point-to-integer narrowing conversions | ||
| (`vfncvt[.rtz].x[u].f.w`) and integer-to-floating-point | ||
| widening conversions (`vfwcvt.f.x[u].v`) become defined when SEW=8. |
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This could be expressed more succinctly by saying something like
Suggested change
| When the Zvfh extension is implemented, all instructions in Sections | |
| <<sec-vector-float>>, <<sec-vector-float-reduce>>, | |
| <<sec-vector-float-reduce-widen>>, <<sec-vector-float-move>>, | |
| <<sec-vfslide1up>>, and <<sec-vfslide1down>> | |
| become defined when SEW=16. | |
| The EEW=16 floating-point operands of these instructions use the binary16 | |
| format. | |
| Additionally, conversions between 8-bit integers and binary16 values are | |
| provided. The floating-point-to-integer narrowing conversions | |
| (`vfncvt[.rtz].x[u].f.w`) and integer-to-floating-point | |
| widening conversions (`vfwcvt.f.x[u].v`) become defined when SEW=8. | |
| When the Zvfh extension is implemented, | |
| for each instruction with an EEW=32 floating-point operand, | |
| a new version is added supporting half the SEW. |
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Indeed. I favor the more explicit version, but we'll see what others say.
topperc
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Mar 17, 2022
Currently we allow half types in vectors if the scalar Zfh extension is enabled. This behavior is not inline with the vector spec. For f32 and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly control the availablity of floating point types in vectors. In order to make our compiler compliant, we either need to remove all support for half in vectors or we need an extension to control it. Draft spec here riscv/riscv-v-spec#780 Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D121345
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Hi, would you mind updating the status about ratification of "zvfhmin". I hope I can enable FP16 vector in GCC upstream. Would you mind telling me when will you ratify "zvfh" extension ? |
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Other FP formats will be supported with other extensions. BF16 is in progress. |
mem-frob
pushed a commit
to draperlaboratory/hope-llvm-project
that referenced
this pull request
Oct 7, 2022
Currently we allow half types in vectors if the scalar Zfh extension is enabled. This behavior is not inline with the vector spec. For f32 and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly control the availablity of floating point types in vectors. In order to make our compiler compliant, we either need to remove all support for half in vectors or we need an extension to control it. Draft spec here riscv/riscv-v-spec#780 Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D121345
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Vector instructions that process IEEE 754 binary16 numbers were included in draft versions of the vector extension, but they were separated from the V extension prior to ratification. This PR adds them back.
The Zvfh extension adds IEEE 754 binary16 support to all FP instructions.
The Zvfhmin extension adds only the conversions to and from binary32.