Trivial fixes to v8

[michaeljclark]

Some very trivial fixes after going through the code several more times.

I'm pushing these changes to riscv-wip which is based on the last upstream rebase. We'll have to revise our branch strategy once we get accepted upstream. After we are upstream (assuming we make it) we should be able to create a stable riscv-qemu-2.12 branch based on upstream master.

riscv-next is actually trailing at the moment given it is the default branch and our proxy for a stable branch. We can revise our branch strategy once we're upstream. i.e. when we have riscv-qemu-2.12, either riscv-qemu-2.12 or master can become the default branch, and we use riscv-wip or riscv-next for integrating new features. At the moment we are targetting changes at the last rebase which presently is qemu-upstream-v8; the pattern we have been using during the upstream review process.

These changes make naming and function interfaces more consistent and lift hardcoded constants (timebase-frequency and clock-frequency) from the device-tree code into header defined constants.

$ ./riscv32-softmmu/qemu-system-riscv32 -cpu help
any-riscv-cpu
rv32gcsu-v1.9.1-riscv-cpu
rv32gcsu-v1.10.0-riscv-cpu
rv32imacu-nommu-riscv-cpu
sifive-e31-riscv-cpu
sifive-u34-riscv-cpu

$ ./riscv32-softmmu/qemu-system-riscv32 -machine help
Supported machines are:
none                 empty machine
sifive_e             RISC-V Board compatible with SiFive E SDK
sifive_u             RISC-V Board compatible with SiFive U SDK
spike_v1.10          RISC-V Spike Board (Privileged ISA v1.10) (default)
spike_v1.9.1         RISC-V Spike Board (Privileged ISA v1.9.1)
virt                 RISC-V VirtIO Board (Privileged ISA v1.10)

$ ./riscv64-softmmu/qemu-system-riscv64 -cpu help
any-riscv-cpu
rv64gcsu-v1.9.1-riscv-cpu
rv64gcsu-v1.10.0-riscv-cpu
rv64imacu-nommu-riscv-cpu
sifive-e51-riscv-cpu
sifive-u54-riscv-cpu

$ ./riscv64-softmmu/qemu-system-riscv64 -machine help
Supported machines are:
none                 empty machine
sifive_e             RISC-V Board compatible with SiFive E SDK
sifive_u             RISC-V Board compatible with SiFive U SDK
spike_v1.10          RISC-V Spike Board (Privileged ISA v1.10) (default)
spike_v1.9.1         RISC-V Spike Board (Privileged ISA v1.9.1)
virt                 RISC-V VirtIO Board (Privileged ISA v1.10)

[michaeljclark]

The changes have ended up being less trivial, albeit safe, as I've been fixing several spec conformance issues. I'm considering spinning a v9 patch series although we are quickly approaching soft-freeze. These could be added to v8 patch series as "bug fixes". i.e. they don't introduce new features.