No representation of predicates in rizin

[Rot127]

Rizin only supports conditionals which are not compatible with the predicate registers of the Hexagon architecture.

The Pu registers are interpreted like this:

If a scalar instruction uses it: The least significant bit determines the truth value. 1 = true, 0 = false.

If a vector instruction uses it: Each bit in the Pu register corresponds to a truth value of a single vector. 1 = true, 0 = false.

The condition, on which the instruction is executed, is stored in RzTypeCond RzAnalysisOp.cond. But non of the types in RzTypeCond match with the interpretation of the Pu register.