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sdram module VHDL file replaced with Verilog.

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1 parent aa742ac commit 4e963012de2d730a79a1e177f8329c144563d71a @rkrajnc committed Feb 29, 2012
Showing with 3 additions and 1 deletion.
  1. +3 −1 fpga/altera/minimig_de1.qsf
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4 fpga/altera/minimig_de1.qsf
@@ -601,7 +601,7 @@ set_global_assignment -name VERILOG_FILE ../../rtl/de1/sseg_decode.v
set_global_assignment -name VERILOG_FILE ../../rtl/de1/sram_ctl.v
set_global_assignment -name VERILOG_FILE ../../rtl/de1/cfide.v
set_global_assignment -name VERILOG_FILE ../../rtl/de1/startram.v
-set_global_assignment -name VHDL_FILE ../../rtl/de1/sdram.vhd
+set_global_assignment -name VERILOG_FILE ../../rtl/de1/sdram.v
set_global_assignment -name VERILOG_FILE ../../rtl/de1/I2C_Controller.v
set_global_assignment -name VERILOG_FILE ../../rtl/de1/I2C_AV_Config.v
set_global_assignment -name VERILOG_FILE ../../rtl/de1/audio_shifter.v
@@ -629,4 +629,6 @@ set_global_assignment -name VERILOG_FILE ../../rtl/minimig/Audio.v
set_global_assignment -name VERILOG_FILE ../../rtl/minimig/Amber.v
set_global_assignment -name VERILOG_FILE ../../rtl/minimig/Agnus.v
set_global_assignment -name VERILOG_FILE ../../rtl/minimig/ActionReplay3.v
+
+
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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