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add files to build ducati (m3) side firmware

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commit 71e27b495bcf6b56cedaff363e974a1cfe76c5ab 1 parent 05b00dd
Rob Clark authored
View
6 .gitignore
@@ -18,3 +18,9 @@ configure
.settings
.dlls
dcetest
+.executables
+.interfaces
+.libraries*
+*.mak
+*.xem3
+ducati/platform/base_image/package
View
5 Makefile.am
@@ -14,11 +14,10 @@ CE_CFLAGS = \
-I$(top_srcdir)/packages/xdctools \
-I$(top_srcdir)/packages/xdais
-libdce_la_SOURCES = dce.c memsrv.c
+libdce_la_SOURCES = dce.c
libdce_la_CFLAGS = -DCLIENT=1 $(WARN_CFLAGS) $(CE_CFLAGS) \
$(SYSLINK_CFLAGS) \
- $(MEMMGR_CFLAGS) \
- $(D2CMAP_CFLAGS)
+ $(MEMMGR_CFLAGS)
libdce_la_LDFLAGS = -no-undefined
libdce_la_LIBADD = $(SYSLINK_LIBS) $(MEMMGR_LIBS) $(D2CMAP_LIBS)
View
234 README
@@ -1,32 +1,220 @@
-WHAT IT IS
-----------
+= About Distributed Codec Engine =
-A library to remotely invoke the hw accellerated codecs on IVA-HD via a
-syslink/rcm shim layer.
+DCE is a library to remotely invoke the hw accellerated codecs on IVA-HD via a syslink/rcm shim layer. This provides access to the [http://processors.wiki.ti.com/index.php/Category:Codec_Engine Codec Engine] codec interface on the coprocessor (ducati/M3) from the host.
-And an interesting project to try on my free time.
+It is similar in purpose to remote codec engine, although at the time RCE was not supported on OMAP4430, and DCE was a simple way to get the same result. They should be roughly interchangeable from the user's perspective, with the caveat that the DCE user should use <code>dce_alloc()</code> and <code>dce_free()</code> to allocate/free the control structures that are passed by pointer to CE APIs.
-HOW TO BUILD
-------------
+DCE is used by:
+* [http://git.mansr.com/?p=omapfbplay omapfbplay]
+* [http://github.com/robclark/gst-ducati gst-ducati]
-Standard autotools build for cortex-a9 side. The shim layer (dce.c) is
-built for both cortex-a9 side (client) and ducati side (server). The rest
-of the bootup code and codec binaries are for now in an internal git tree
-(linked as a submodule) until standalone codec libraries are made
-available.
+If you are using DCE (for anything that can be revealed publicly) let me know and I'll add a link.
-The corresponding ducati appm3 image (dce_app_m3.xem3) is found in the
-firmware directory. The Notify_MPUSYS_reroute_Test_Core0.xem3 from syslink
-build should be used for sysm3 image. The dce_app_m3.xem3 replaces the
-official base_image_app_m3.xem3.
+:Note: look in the README file for the latest version of this document, in particular for the required versions of various dependent components and tools, as these can change over time
-Note that for now the checked in dce_app_m3.xem3 only contains h264 and
-mpeg4 decoders. The other codecs are still only available with a proper
-SLA in place. Contact your TI representative.
+A pre-built ducati appm3 image (''dce_app_m3.xem3'') is found in the firmware directory. The ''Notify_MPUSYS_reroute_Test_Core0.xem3'' from syslink build should be used for sysm3 image. The ''dce_app_m3.xem3'' replaces the official OpenMAX ''base_image_app_m3.xem3''.
-TODO
-----
-Migrate to newer syslink with RcmServer thread pool, to allow for using
-more than one codec instance at a time.
+= How To Build =
+
+These instructions are assuming you are cross-compiling on a linux machine for ducati/M3 coprocessor side and natively building the linux/A9 host side (although the instructions for cross-compiling the host side are roughly the same).
+
+The following gives an example of how to build. I don't claim that it is the best or only way. But these are the versions I am currently using:
+
+* TMS470/ARM Code Generation Tools (CGT) - 4.6.1
+* XDC tools - 3.20.07.86
+* BIOS (the RTOS) - 6.31.03.25
+* Codec Engine (CE) - 3.20.00.16
+* Framework Component (FC) - 3.20.00.22
+* XDAIS - 7.20.00.07
+* HDVICP2 API and HDVICP2_CODECS - 1.00.000
+* bios-syslink - commit-id [https://gitorious.org/bios-syslink/bios-syslink/commit/48e98007e21e311c126f89ff51616bf6d7067b9d 48e98007e21e311c126f89ff51616bf6d7067b9d]
+* libdce
+
+On linux side, the following versions are used:
+
+* kernel ... 2.6.38 linaro kernel plus ???
+** for now I am using: [https://github.com/robclark/kernel-omap4/tree/ti-omap4-drm/ git://github.com/robclark/kernel-omap4.git ti-omap4-drm branch]
+* syslink userspace: syslink-2.0
+* tiler/memmgr userspace: memmgr_2.0
+
+
+== Building Ducati/M3 Side ==
+
+=== Install TMS470/ARM Compiler ===
+
+Install Code Generation Tools (CGT) from:
+
+* https://www-a.ti.com/downloads/sds_support/CodeGenerationTools.htm
+
+Install to ''$HOME/ducati/ti_cgt_tms470_<version>''
+
+=== Install XDC tools ===
+
+Download XDC tools from:
+
+* http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/rtsc
+
+Install to ''$HOME/ducati/xdctools_<version>''
+
+=== Install BIOS ===
+
+Download BIOS (the RTOS) from:
+
+* http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/index.html
+
+Install to ''$HOME/ducati/bios_<version>''
+
+=== Install Codec Engine ===
+
+Download Codec Engine (CE) from:
+
+* http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ce/
+
+The lite version is fine. Install to ''$HOME/ducati/codec_engine_<version>''
+
+=== Install Framework Components ===
+
+Download Framework Components (FC) from:
+
+* http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/fc
+
+The lite version without fctools is fine. Install to ''$HOME/ducati/framework_components_<version>''
+
+=== Install XDAIS ===
+
+Download XDAIS from:
+
+* http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/xdais/index.html
+
+Untar to ''$HOME/ducati/xdais_<version>''
+
+=== Install HDVICP2 library codecs ===
+
+Install HDCICP2 plus desired codecs from:
+
+* http://software-dl.ti.com/dsps/dsps_public_sw/codecs/HDVICP2/index_FDS.html
+
+Install to ''$HOME/ducati/'', and then untar each of the .tar files that was installed.
+
+ cd $HOME/ducati
+ for f in ivahd_*.tar; do
+ untar xf $f
+ done
+
+you should end up with:
+
+* ''$HOME/ducati/ivahd_hdvicp20api_01_00_00_19_production''
+* ''$HOME/ducati/ivahd_h264dec_01_00_00_00_production''
+* ''$HOME/ducati/ivahd_mpeg2vdec_01_00_00_00_production''
+* ''$HOME/ducati/ivahd_jpegvdec_01_00_00_00_production''
+
+=== Setup Environment ===
+
+Setup environment variables needed for the build steps:
+
+ export TMS470_C_DIR="$HOME/ducati/ti_cgt_tms470_4_6_1/include;$HOME/ducati/ti_cgt_tms470_4_6_1/lib"
+ export TMS470CGTOOLPATH="$HOME/ducati/ti_cgt_tms470_4_6_1"
+ XDCPATH=""
+ for f in $HOME/ducati/*/packages; do
+ XDCPATH="$XDCPATH$f;"
+ done
+ export XDCPATH
+ export XDCROOT="$HOME/ducati/xdctools_3_20_07_86"
+ export XDCARGS="profile=release"
+
+Note: if you are using different version numbers, the paths would have to be adjusted accordingly.
+
+=== Build Syslink ===
+
+Clone syslink tree in ''$HOME/ducati/bios-syslink''
+
+ cd $HOME/ducati
+ git clone git://gitorious.org/bios-syslink/bios-syslink.git
+ cd bios-syslink/packages
+ git checkout 48e98007e21e311c126f89ff51616bf6d7067b9d
+
+ export XDCBUILDCFG="`pwd`/config.bld"
+ $XDCROOT/xdc clean -PR ./ti
+ $XDCROOT/xdc -PR ./ti/sdo ./ti/omap/uart/ ./ti/omap/mem/ ./ti/omap/platform/ ./ti/omap/slpm/ ./ti/omap/deh ./ti/omap/hdmiwa
+ $XDCROOT/xdc -PR ./ti/omap/samples/notify
+
+when the build succeeds, the sysm3 image will be in ''ti/omap/samples/notify/ti_omap_platform_core0/release/Notify_MPUSYS_reroute_Test_Core0.xem3''.
+
+Note: for now, instead of git://git.omapzoom.org/platform/hardware/ti/bios-syslink.git we use the gitorious tree. There are some kernel patches missing in ubuntu/linaro 2.6.38 kernel (for now) which are needed to use latest official tree. (Probably the missing patch is [http://review.omapzoom.org/#change,13113 this].)
+
+Note: if you change syslink, you need to rebuild libdce.. when you build syslink you build both the sysm3 image, plus syslink libraries used by the appm3 image.
+
+=== Build DCE ===
+
+Clone libdce tree in ''$HOME/ducati/libdce''
+
+ cd $HOME/ducati
+ git clone git://github.com/robclark/libdce.git
+ cd libdce
+
+ export XDCBUILDCFG="`pwd`/ducati/build/config.bld"
+ cd ducati/platform/base_image
+ $XDCROOT/xdc -j4 -PD .
+
+when the build succeeds, the appm3 image will be in ''out/app_m3/release/dce_app_m3.xem3''.
+
+Note, to reduce the size of the images, the debug symbols can be stripped:
+
+ $TMS470CGTOOLPATH/bin/strip470 Notify_MPUSYS_reroute_Test_Core0.xem3
+ $TMS470CGTOOLPATH/bin/strip470 dce_app_m3.xem3
+
+== Building Linux/A9 side: ==
+
+Standard autotools build for cortex-a9 side userspace components.
+
+* kernel: 2.6.38 linaro kernel
+** .. patches ..
+* tiler:
+** git://git.omapzoom.org/platform/hardware/ti/tiler.git
+** branch: memmgr_2.0
+* syslink:
+** git://git.omapzoom.org/platform/hardware/ti/syslink.git
+** branch: syslink-2.0
+
+=== Build TILER userspace ===
+
+ git clone git://git.omapzoom.org/platform/hardware/ti/tiler.git
+ cd tiler
+ git checkout origin/memmgr_2.0
+ ./bootstrap.sh
+ ./configure --prefix=/usr
+ make -j4
+ sudo make install
+
+=== Build Syslink userspace ===
+
+Ignore the build instructions in syslink tree if you are building natively. Too much to read..
+
+ git clone git://git.omapzoom.org/platform/hardware/ti/syslink.git
+ cd syslink/syslink
+ git checkout origin/syslink-2.0
+ ./bootstrap.sh
+ ./configure --prefix=/usr
+ make -j4
+ sudo make install
+
+== Build DCE userspace ==
+
+If building natively, clone libdce tree. Otherwise if cross-compiling you can use same copy you cloned on your PC when you build ''dce_app_m3.xem3''.
+
+ cd libdce
+ ./autogen --prefix=/usr
+ make -j4
+ sudo make install
+
+= Useful Links =
+
+* http://www.omappedia.org/wiki/Syslink_Project
+* http://www.omappedia.org/wiki/Syslink_3 - the future..
+
+= TODO =
+
+* update instructions about syslink and TILER version dependencies.. and add instructions for building ducati image.
+* migrate to syslink v3.0
View
5 configure.ac
@@ -50,10 +50,7 @@ dnl Check for syslink
PKG_CHECK_MODULES([SYSLINK], [syslink])
dnl Check for tiler memmgr
-PKG_CHECK_MODULES([MEMMGR], [libmemmgr])
-
-dnl Check for d2cmap
-PKG_CHECK_MODULES([D2CMAP], [libd2cmap])
+PKG_CHECK_MODULES([MEMMGR], [libtimemmgr])
dnl *** checks for header files ***
dnl check if we have ANSI C header files
View
38 dce.c
@@ -195,7 +195,6 @@ static void dce_clean(void *ptr)
typedef struct {
Int pid; /* value of zero means unused */
Int refs;
- RcmClient_Handle handle;
Engine_Handle engines[10]; /* adjust size per max engines per client */
VIDDEC3_Handle codecs[10]; /* adjust size per max codecs per client */
} Client;
@@ -231,36 +230,12 @@ static void dce_register_engine(Int pid, Engine_Handle engine)
}
}
} else {
- int err;
- char name[20];
- RcmClient_Params params = {0};
-
c = get_client(0);
if (!c) {
ERROR("too many clients");
goto out;
}
- snprintf (name, DIM(name), "memsrv-%08x", pid);
- INFO("creating mem client: %p (%s)", c, name);
-
- RcmClient_init();
- RcmClient_Params_init(&params);
-
- params.heapId = 1; // XXX 1==appm3, but would be nice not to hard-code
-
- err = RcmClient_create(name, &params, &c->handle);
- if (err < 0) {
- ERROR("fail: %08x", err);
- return;
- }
-
- err = MemMgr_RegisterRCMClient(pid, c->handle);
- if (err < 0) {
- ERROR("fail: %08x", err);
- return;
- }
-
c->pid = pid;
c->refs = 1;
c->engines[0] = engine;
@@ -292,8 +267,6 @@ static void dce_unregister_engine(Int pid, Engine_Handle engine)
c->refs--;
if (! c->refs) {
- INFO("deleting mem client: %p", c);
- RcmClient_delete(&c->handle);
c->pid = 0;
}
}
@@ -943,14 +916,10 @@ int dce_deinit(void)
static pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
static int count = 0;
-int memsrv_init (char *name);
-int memsrv_deinit (void);
-
static void init(void)
{
int err;
Ipc_Config config = {0};
- char name[20];
pthread_mutex_lock(&mutex);
@@ -966,10 +935,6 @@ static void init(void)
DEBUG("Ipc_setup() -> %08x", err);
pid = getpid();
- snprintf (name, DIM(name), "memsrv-%08x", pid);
-
- err = memsrv_init(name);
- DEBUG("memsrv_init() -> %08x", err);
err = dce_init();
DEBUG("dce_init() -> %08x", err);
@@ -993,9 +958,6 @@ static void deinit(void)
err = dce_deinit();
DEBUG("dce_deinit() -> %08x", err);
- err = memsrv_deinit();
- DEBUG("memsrv_deinit() -> %08x", err);
-
err = Ipc_destroy();
DEBUG("Ipc_destroy() -> %08x", err);
View
4 dce_priv.h
@@ -33,8 +33,8 @@
#ifndef __DCE_PRIV_H__
#define __DCE_PRIV_H__
-#ifndef CLIENT
-# define SERVER 1
+#if !(defined(CLIENT) || defined(SERVER))
+# error "Must define either CLIENT or SERVER"
#endif
int dce_init(void);
View
282 ducati/build/common.bld
@@ -0,0 +1,282 @@
+/*
+ * Copyright 2009 by Texas Instruments Incorporated.
+ *
+ * All rights reserved. Property of Texas Instruments Incorporated.
+ * Restricted rights to use, duplicate or disclose this code are
+ * granted through contract.
+ *
+ */
+
+/*
+ * ======== common.bld ========
+ *
+ */
+
+
+/*
+ * ======== getCores ========
+ * Determines which cores to build for.
+ *
+ * Any argument in XDCARGS which does not contain core= is treated
+ * as a core name. This way build for multiple cores can be specified by
+ * separating them with a space.
+ */
+function getCores(xdcArgs)
+{
+ var coreNames = new Array();
+
+ /* Check for any XDCARGS with core=; these are the corenames */
+ for (var i = 0; i < xdcArgs.length; i++) {
+ if (xdcArgs[i].match(/core=/)) {
+ coreNames.push(xdcArgs[i].substr(5));
+ }
+ }
+
+ return coreNames;
+}
+
+
+/*
+ * ======== getProfiles ========
+ * Determines which profiles to build for.
+ *
+ * Any argument in XDCARGS which does not contain platform= is treated
+ * as a profile. This way multiple build profiles can be specified by
+ * separating them with a space.
+ */
+function getProfiles(xdcArgs)
+{
+ var profiles = new Array();
+
+ /* Check for any XDCARGS with profile=; these are profiles. */
+ for (var i = 0; i < xdcArgs.length; i++) {
+ if (xdcArgs[i].match(/profile=/)) {
+ profiles.push(xdcArgs[i].substr(8));
+ }
+ }
+
+ return profiles;
+}
+
+function getBuildModes(xdcArgs)
+{
+ var buildModes = new Array();
+
+ /* Check for any XDCARGS with buildMode=; these are specific
+ build configuration */
+ for (var i = 0; i < xdcArgs.length; i++) {
+ if (xdcArgs[i].match(/buildMode=/)) {
+ buildModes.push(xdcArgs[i].substr(10));
+ }
+ }
+ return buildModes;
+}
+
+
+/*
+ * ======== getTraceType ========
+ * Determines which trace type to build for.
+ *
+ * Any argument in XDCARGS which does not contain trace_type= is treated
+ * as a trace type name. This way build for different trace type can be specified by
+ * separating them with a space.
+ * XDCARGS="profile=debug core=app_m3 target_build=BUILD_OMAP4 trace_type=UIA_SW_ON"
+ */
+function getTraceType(xdcArgs)
+{
+ var trace_type = new Array();
+
+ /* Check for any XDCARGS with trace_type=; these are the corenames */
+ for (var i = 0; i < xdcArgs.length; i++) {
+ if (xdcArgs[i].match(/trace_type=/)) {
+ trace_type.push(xdcArgs[i].substr(11));
+ }
+ }
+
+ return trace_type;
+}
+
+
+/*
+ * ======== getTraceMode ========
+ * Determines which trace mode to use.
+ *
+ */
+function getTraceMode(xdcArgs)
+{
+ var trace = new Array();
+
+ /* Check for any XDCARGS with profile=; these are profiles. */
+ for (var i = 0; i < xdcArgs.length; i++) {
+ if (xdcArgs[i].match(/trace=/)) {
+ trace.push(xdcArgs[i].substr(6));
+ }
+ }
+
+ return trace;
+}
+
+// Possible options - none Virtio
+// ISS_SIMULATOR
+// VIRTIO
+// ...
+function getTargetEnvironment(xdcArgs)
+{
+ var target_env = new Array();
+
+ /* Check for any XDCARGS with profile=; these are profiles. */
+ for (var i = 0; i < xdcArgs.length; i++) {
+ if (xdcArgs[i].match(/target_env=/)) {
+ target_env.push(xdcArgs[i].substr(11));
+ }
+ }
+ return target_env;
+}
+
+function buildOptions(xdcArgs, aCompileOpts, coreName)
+{
+ var buildMode = new Array();
+
+ var buildMode = getBuildModes(xdcArgs);
+
+ var compileOpts = " -D_DM270 -D_DM290_IMX_MCFIX_ -DSERVER=1 --gcc";
+
+ if (aCompileOpts != null){
+ compileOpts += aCompileOpts;
+ }
+
+ /*Update compile opt if trace is uart*/
+ var traceMode = getTraceMode(xdcArgs);
+ if(traceMode.length != 0)
+ {
+ if(traceMode[0].match("UART"))
+ {
+ compileOpts += " -DUART_TRACES ";
+ }
+ }
+
+ if(coreName != null) {
+ if(coreName.match(/sys_m3/)){
+ compileOpts += " -DDUCATI_SYS_M3 ";
+ }
+
+ if(coreName.match(/app_m3/)){
+ compileOpts += " -DDUCATI_APP_M3 ";
+ }
+ }
+
+ return compileOpts;
+}
+
+
+
+/*
+ * ======== buildLibs ========
+ * This function generates the makefile goals for the libraries taking
+ * into account the profile variants, specific ducati cores and build modes
+ *
+ */
+function buildLibs(objList, trgList, xdcArgs, libCompileOpts, coreName)
+{
+ var compileOpts = buildOptions(xdcArgs, libCompileOpts, coreName);
+ var profiles = getProfiles(xdcArgs);
+ //print ("profile length" + profiles.length +"\t" + "profile0" + profiles[0] +"\n");
+ /* If no profiles were assigned, build for whole program debug */
+ if (profiles.length == 0) {
+ profiles[0] = "whole_program_debug";
+ }
+
+ for (var i = 0; i < Build.targets.length; i++) {
+
+ var targ = Build.targets[i];
+
+ for (var j = 0; j < profiles.length; j++) {
+
+ var profile = profiles[j];
+ var profileOpts = compileOpts;
+
+ if (profile.match(/release/)) {
+ profileOpts += " -O3";
+ }
+
+ if (coreName == null) {
+ var lib_name = 'lib/' + profile + '/' + Pkg.name ;
+ }
+ else {
+ var lib_name = 'lib/' + coreName + '/' + profile + '/' + Pkg.name ;
+ }
+
+ var lib = Pkg.addLibrary(lib_name, targ, {profile: profile, copts: profileOpts});
+
+ lib.addObjects(objList);
+ }
+ }
+}
+
+/*
+ * ======== supportsCore ========
+ * Returns true if coreName is in the supported core list. If coreNameList
+ * is null or empty, that's taken to mean all targets are supported.
+ */
+function supportsCore(coreName, coreNameList)
+{
+ if ((coreNameList == null) || (coreNameList.length == 0)) {
+ return true;
+ }
+
+ for (var j = 0; j < coreNameList.length; j++) {
+ if(coreName.match(coreNameList[j])){
+ return true;
+ }
+ }
+
+ return false;
+}
+
+/*
+ * ======== commonGetLibs ========
+ * Common getLibs function
+ */
+
+function commonGetLibs(prog, bCoreFlag, pkg, dir)
+{
+ var suffix;
+
+ /* find a compatible suffix */
+ if ("findSuffix" in prog.build.target) {
+ suffix = prog.build.target.findSuffix(pkg);
+ }
+ else {
+ suffix = prog.build.target.suffix;
+ }
+
+ var name = pkg.$name + ".a" + suffix;
+ var lib = "";
+
+ if (bCoreFlag == true) {
+ lib = "lib/" + prog.global.coreName + "/" + pkg.profile + "/" + name;
+ }
+ else {
+ lib = "lib/" + "/" + pkg.profile + "/" + name;
+ }
+
+ if (java.io.File(dir + lib).exists()) {
+ return lib;
+ }
+ else {
+ print("Default lib not found: " + lib +"\nlooking for release lib");
+ if (bCoreFlag == true) {
+ lib = "lib/" + prog.global.coreName + "/" + "release/" + name;
+ }
+ else {
+ lib = "lib/" + "/" + "release/" + name;
+ }
+ if (java.io.File(dir + lib).exists()) {
+ return lib;
+ }
+ }
+
+ /* could not find any library, throw exception */
+ throw Error("Library not found: " + lib);
+}
+
View
28 ducati/build/config.bld
@@ -0,0 +1,28 @@
+
+var Build = xdc.useModule('xdc.bld.BuildEnvironment');
+
+var commonBld = xdc.loadCapsule("ducati/build/common.bld");
+var commonOpts = "-g";
+
+xdc.loadCapsule("ducatiplatform.xs");
+
+/************************************
+* Setup for M3 target
+************************************/
+var M3 = xdc.useModule('ti.targets.arm.elf.M3');
+M3.rootDir = java.lang.System.getenv("TMS470CGTOOLPATH");
+M3.ccOpts.suffix += " --gcc -D___DSPBIOS___ -D___DUCATI_FW___ -DBN_DEBUG__PASS_THRU";
+M3.ccOpts.suffix += " -ms ";
+M3.ccOpts.suffix += commonOpts;
+M3.lnkOpts.suffix += " -x ";
+M3.lnkOpts.prefix += " --zero_init=off ";
+//set default platform and list of all interested platforms for M3
+M3.platforms = ["ti.platforms.generic:DucatiPlatform"];
+M3.platform = M3.platforms[0];
+
+Build.targets = [
+ M3,
+ ];
+
+var Pkg = xdc.module("xdc.bld.PackageContents");
+
View
111 ducati/build/ducatiplatform.xs
@@ -0,0 +1,111 @@
+var memory = [];
+
+
+//0.984275MB memory for sysM3 code in I/D bus cached region
+memory[0] = ["MEM_CODE_SYSM3",
+{
+ name: "MEM_CODE_SYSM3",
+ base: 0x4000,
+ len: 0x000FC000,
+ space: "code"
+}];
+
+//3MB memory for appM3 code section in I/D bus cached region
+memory[1] = ["MEM_CODE_APPM3",
+{
+ name: "MEM_CODE_APPM3",
+ base: 0x00100000,
+ len: 0x00300000,
+ space: "code"
+}];
+
+//12MB memory section for appM3 heap in I/D bus cached region
+memory[2] = ["MEM_HEAP1_APPM3",
+{
+ name: "MEM_HEAP1_APPM3",
+ base: 0x00400000,
+ len: 0x00C00000,
+ space: "data"
+}];
+
+
+//0.25MB memory for sysM3 const section in S bus cached region
+memory[3] = ["MEM_CONST_SYSM3",
+{
+ name: "MEM_CONST_SYSM3",
+ base: 0x80000000,
+ len: 0x00040000,
+ space: "data"
+}];
+
+//0.75MB memory section for sysM3 heap in S bus cached region
+memory[4] = ["MEM_HEAP_SYSM3",
+{
+ name: "MEM_HEAP_SYSM3",
+ base: 0x80040000,
+ len: 0x000C0000,
+ space: "data"
+}];
+
+//1.5MB memory for appM3 const section in S bus cached region
+memory[5] = ["MEM_CONST_APPM3",
+{
+ name: "MEM_CONST_APPM3",
+ base: 0x80100000,
+ len: 0x00200000,
+ space: "data"
+}];
+
+//(~29.375MB) memory section for appM3 heap in S bus cached region
+memory[6] = ["MEM_HEAP2_APPM3",
+{
+ name: "MEM_HEAP2_APPM3",
+ base: 0x80300000,
+ len: 0x01CE0000,
+ space: "data"
+}];
+
+//128KB For Trace Buffer
+memory[7] = ["DUCATI_TRACE_BUFFER",
+{
+ name: "DUCATI_TRACE_BUFFER",
+ base: 0x81FE0000,
+ len: 0x20000,
+ space: "data"
+}];
+
+//336KB memory for IPC memory in S bus non cached region
+memory[8] = ["MEM_IPC_HEAP0",
+{
+ name: "MEM_IPC_HEAP0",
+ base: 0xA0000000,
+ len: 0x54000,
+ space: "data"
+}];
+
+//688KB memory for IPC memory in S bus non cached region
+memory[9] = ["MEM_IPC_HEAP1",
+{
+ name: "MEM_IPC_HEAP1",
+ base: 0xA0054000,
+ len: 0xAC000,
+ space: "data"
+}];
+
+memory[10] = ["L2_ROM",
+{
+ name: "L2_ROM",
+ base: 0x0,
+ len: 0x4000,
+ space: "code/data"
+}];
+
+Build.platformTable["ti.platforms.generic:DucatiPlatform"] =
+{
+ clockRate: 200.0,
+ catalogName: "ti.catalog.arm.cortexm3",
+ deviceName: "OMAP4430",
+ mem: memory,
+ customMemoryMap: memory
+};
+
View
401 ducati/platform/base_image/dce_app_m3.cfg
@@ -0,0 +1,401 @@
+var Startup = xdc.useModule('xdc.runtime.Startup');
+var Program = xdc.useModule('xdc.cfg.Program');
+
+Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+Cache.enableCache = true;
+
+var m3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+m3Hwi.enableWA1_1 = false;
+Program.global.cacheMode = "WA_DISABLED"; // from XDCARGS, this flag won't be defined.
+//Set Core ID for the processor
+var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.id = 1;
+
+var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
+var params = new GateMutexPri.Params;
+
+Program.stack = 0x800;
+Program.global.gOSALgate = GateMutexPri.create(params);
+Program.global.coreName = "app_m3";
+Program.global.targetBuild = "BUILD_OMAP4";
+
+Program.global.dstProcId = 2; //For SysM3
+//configure BIOS
+BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.clockEnabled = true;
+BIOS.rtsGateType = BIOS.GateHwi;
+var m3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+m3Hwi.vectorTableAddress = 0x0;
+m3Hwi.enableException = true;
+
+var Exception = xdc.useModule('ti.sysbios.family.arm.m3.Exception');
+Exception.doPrint = true;
+
+
+//XDC runtime configuration
+xdc.useModule('xdc.runtime.knl.Semaphore').Proxy = xdc.useModule('ti.sysbios.xdcruntime.SemProcessSupport');
+
+/*
+* Create a static task for app M3 intialization functions
+*/
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 0x4000;
+var task_params = new Task.Params;
+task_params.stackSize = 0x4000;
+task_params.instance.name = "Ducati_AppTask";
+Task.create("&Ducati_AppTask", task_params);
+
+
+Task.common$.namedInstance = true;
+var Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+var Swi = xdc.useModule('ti.sysbios.knl.Swi');
+//I2C
+var hwiparams6 = new Hwi.Params;
+hwiparams6.arg = 1;
+
+var hwiparams7 = new Hwi.Params;
+hwiparams7.arg = 2;
+
+
+/*
+* Create a default system heap using ti.bios.HeapMem and plugin this as default heap
+*/
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var GateHwi = xdc.useModule('ti.sysbios.gates.GateHwi');
+var heapMemParams = new HeapMem.Params;
+
+HeapMem.common$.gate = GateHwi.create();
+
+heapMemParams.size = 0xBFFFEA;
+heapMemParams.sectionName = ".systemHeap";
+var heap0 = HeapMem.create(heapMemParams);
+Memory.defaultHeapInstance = heap0;
+Program.global.heap0 =heap0;
+/*
+/* Heap For Video Components */
+var HeapMemVideo = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var heapMemParamsVideo = new HeapMemVideo.Params;
+
+heapMemParamsVideo.size = 0x1CDFFEA;
+heapMemParamsVideo.sectionName = ".HeapVideo";
+var heapvideo = HeapMem.create(heapMemParamsVideo);
+Program.global.heap1 = heapvideo;
+
+/*
+* Do section mapping to memory regions
+*/
+Program.sectMap["__TI_handler_table"] = "MEM_CONST_APPM3";
+Program.sectMap[".data"] = "MEM_CODE_APPM3";
+Program.sectMap[".text"] = "MEM_CODE_APPM3";
+Program.sectMap[".cinit"] = "MEM_CODE_APPM3";
+Program.sectMap[".const"] = "MEM_CONST_APPM3";
+Program.sectMap[".pinit"] = "MEM_CODE_APPM3";
+Program.sectMap[".args"] = "MEM_CODE_APPM3";
+Program.sectMap[".rodata"] = "MEM_CODE_APPM3";
+Program.sectMap[".neardata"] = "MEM_CODE_APPM3";
+Program.sectMap[".bss"] = "MEM_CODE_APPM3";
+Program.sectMap[".sysmem"] = "MEM_CONST_APPM3";
+Program.sectMap[".HeapVideo"] = "MEM_HEAP2_APPM3";
+Program.sectMap[".systemHeap"] = "MEM_HEAP1_APPM3";
+Program.sectMap[".stack"] = "MEM_CODE_APPM3";
+Program.sectMap[".stackMemory"] = "MEM_CODE_APPM3";
+Program.sectMap[".taskStackSection"] = "MEM_CODE_APPM3";
+Program.sectMap["mmsdbgvarlist"] = "MEM_CODE_APPM3";
+Program.sectMap["halSubModules"] = "MEM_CODE_APPM3";
+Program.sectMap[".lens_none_ld_hdl"] = "MEM_CODE_APPM3";
+Program.sectMap[".awb_scratch"] = "MEM_CODE_APPM3";
+Program.sectMap["tools_log_buffer"] = "MEM_CODE_APPM3";
+//codec specific memory map
+Program.sectMap[".H264ENC_TI_DTCM1_STATIC_DATA"] = "MEM_CODE_APPM3";
+Program.sectMap[".H264ENC_TI_DTCM2_STATIC_DATA"] = "MEM_CODE_APPM3";
+Program.sectMap[".H264ENC_TI_NonDeterministicDescriptors_sect"] = "MEM_CODE_APPM3";
+Program.sectMap[".H264ENC_TI_sH264CalcTables"] = "MEM_CODE_APPM3";
+Program.sectMap[".H264ENC_TI_CONST_EXT_SL2_sect"] = "MEM_CODE_APPM3";
+Program.sectMap[".H264ENC_TI_IlfMbctTabs_sect"] = "MEM_CODE_APPM3";
+Program.sectMap[".H264VENC_TI_CabacContexts_sect"] = "MEM_CODE_APPM3";
+Program.sectMap[".H264ENC_TI_MEFastME01BFrameAlgo_sect"] = "MEM_CODE_APPM3";
+Program.sectMap[".H264ENC_TI_MEFastME01PFrameAlgo_sect"] = "MEM_CODE_APPM3";
+Program.sectMap[".H264ENC_TI_DTCM_sect"] = "MEM_CODE_APPM3";
+Program.sectMap[".load_data"] = "MEM_CONST_APPM3";
+Program.sectMap[".VP6_LOAD_DATA11"] = "MEM_CONST_APPM3";
+Program.sectMap[".VP6_LOAD_DATA12"] = "MEM_CONST_APPM3";
+Program.sectMap[".VP6_LOAD_DATA21"] = "MEM_CONST_APPM3";
+Program.sectMap[".VP6_LOAD_DATA22"] = "MEM_CONST_APPM3";
+Program.sectMap[".VP6DEC_TI_dSect1"] = "MEM_CONST_APPM3";
+Program.sectMap[".VP6DEC_TI_dSect2"] = "MEM_CONST_APPM3";
+Program.sectMap[".VP6_ilf_pstack"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP6_Ecd3LseCmdTable"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP6_Calc3LseCmdTable"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP6_Mc3LseCmdTable"] = "MEM_CODE_APPM3";
+//Program.sectMap[".VP7_LOAD_DATA"] = "MEM_CONST_APPM3";
+Program.sectMap[".VP7DEC_TI_dSect1"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7DEC_TI_dSect2"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7VDEC_STATIC_TABLE1"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7VDEC_STATIC_TABLE2"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7VDEC_STATIC_TABLE3"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7VDEC_STATIC_TABLE4"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7VDEC_STATIC_TABLE5"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7_LOAD_DATA1_1"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7_LOAD_DATA1_2"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7_LOAD_DATA1_3"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7_LOAD_DATA1_4"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7_LOAD_DATA2_1"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7_LOAD_DATA2_2"] = "MEM_CODE_APPM3";
+Program.sectMap[".VP7_LOAD_DATA2_3"] = "MEM_CODE_APPM3";
+
+Program.sectMap[".MPEG4VENC_TI_ICONT1_DataSect0"] = "MEM_CODE_APPM3";
+Program.sectMap[".MPEG4VENC_TI_ICONT1_DataSect1"] = "MEM_CODE_APPM3";
+Program.sectMap[".MPEG4VENC_TI_ICONT1_DataSect2"] = "MEM_CODE_APPM3";
+Program.sectMap[".MPEG4VENC_TI_ICONT2_DataSect0"] = "MEM_CODE_APPM3";
+Program.sectMap[".MPEG4VENC_TI_ICONT2_DataSect1"] = "MEM_CODE_APPM3";
+Program.sectMap[".MPEG4VENC_TI_ICONT2_DataSect2"] = "MEM_CODE_APPM3";
+Program.sectMap[".MPEG4VENC_TI_ICONT2_DataSect3"] = "MEM_CODE_APPM3";
+Program.sectMap[".text: { *<copy*>(.text) }"] = "MEM_CODE_APPM3";
+
+Program.sectMap[".load_data1"] = "MEM_CONST_APPM3";
+Program.sectMap[".load_data2"] = "MEM_CONST_APPM3";
+Program.sectMap[".load_data3"] = "MEM_CONST_APPM3";
+Program.sectMap[".load_data4"] = "MEM_CONST_APPM3";
+Program.sectMap[".load_data5"] = "MEM_CONST_APPM3";
+Program.sectMap[".load_data6"] = "MEM_CONST_APPM3";
+Program.sectMap[".load_static_tbls"] = "MEM_CONST_APPM3";
+
+//Program.sectMap[".Ipc_ToHostConfig"] = {loadSegment: "MEM_IPC_SHMEM"};
+
+
+var GateMutex = xdc.useModule('ti.sysbios.gates.GateMutex');
+var GateMP = xdc.useModule('ti.sdo.ipc.GateMP');
+xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+
+// configuring multiproc module
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+MultiProc.setConfig("AppM3", ["Tesla", "AppM3", "SysM3", "MPU"]);
+
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+Ipc.procSync = Ipc.ProcSync_PAIR;
+/* Settings for Ipc synchronization */
+for (var i=0; i < MultiProc.numProcessors; i++) {
+ Ipc.setEntryMeta({
+ remoteProcId: i,
+ });
+}
+
+var InterruptDucati = xdc.useModule('ti.sdo.ipc.family.omap4430.InterruptDucati');
+InterruptDucati.ducatiCtrlBaseAddr = 0x40001000;
+InterruptDucati.mailboxBaseAddr = 0xAA0F4000;
+
+var GateHWSpinLock = xdc.useModule('ti.sdo.ipc.gates.GateHWSpinlock');
+GateHWSpinLock.baseAddr = 0xAA0F6800;
+
+var Notify = xdc.useModule('ti.sdo.ipc.Notify');
+Notify.numEvents = 32;
+
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+
+var Deh = xdc.useModule('ti.omap.deh.Deh');
+
+/* IPC Shared Memory Map */
+Program.global.SHAREDMEM = 0xA0000000;
+Program.global.SHAREDMEMSIZE = 0x54000;
+
+SharedRegion.setEntryMeta(0,
+ { base: Program.global.SHAREDMEM,
+ len: Program.global.SHAREDMEMSIZE,
+ ownerProcId: 3,
+ isValid: true,
+ cacheEnable: false,
+ name: "ipc_shm",
+ });
+
+Program.global.SHAREDMEM2 = 0xA0054000;
+Program.global.SHAREDMEMSIZE2 = 0x000AC000;
+
+SharedRegion.setEntryMeta(1,
+ { base: Program.global.SHAREDMEM2,
+ len: Program.global.SHAREDMEMSIZE2,
+ ownerProcId: 3,
+ isValid: true,
+ cacheEnable: false,
+ createHeap: true,
+ name: "ipc_shm2",
+ });
+
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+MessageQ.numHeaps = 2;
+
+var RcmServer = xdc.useModule('ti.sdo.rcm.RcmServer');
+var RCM = xdc.useModule('ti.sdo.rcm.RcmClient'); //APP CLIENT
+Program.global.dstProcId = 2;
+
+/* specify which ipc layer to use */
+var Settings = xdc.useModule('ti.sdo.rcm.Settings');
+Settings.ipc = Settings.IpcSupport_ti_sdo_ipc;
+
+/*
+ * Trace Settings
+ */
+
+xdc.useModule('ti.sysbios.xdcruntime.Settings');
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+/* LoggerSys uses System_printf for routing log events */
+var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
+var LoggerSysParams = new LoggerSys.Params();
+
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Main = xdc.useModule('xdc.runtime.Main');
+var debug = false; // change this to get traces..
+if (debug) {
+ Defaults.common$.diags_ENTRY = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_EXIT = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_LIFECYCLE = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_INTERNAL = Diags.RUNTIME_ON; // needed for asserts
+ Defaults.common$.diags_ASSERT = Diags.RUNTIME_ON; // development only
+ Defaults.common$.diags_STATUS = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_USER1 = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_USER2 = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_USER3 = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_USER4 = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_USER5 = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_USER6 = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_INFO = Diags.RUNTIME_OFF;
+ Defaults.common$.diags_ANALYSIS = Diags.RUNTIME_OFF;
+ /* default buffer size isn't big enough if we are
+ * enabling some debug traces
+ */
+ SysMin.bufSize = 40960;
+}
+Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
+System.SupportProxy = SysMin;
+/* this hooks up System_printf() to syslink trace daemon..
+ * note that even though we aren't using the uart, the
+ * SysMinToTraceBuffer fxns are in the UART driver.. :-/
+ */
+xdc.useModule('ti.omap.uart.Uartdrv');
+SysMin.outputFxn = "&SysMinToTraceBuffer_copy";
+Startup.firstFxns.$add("&SysMinToTraceBuffer_init");
+
+
+/* create the semaphore (event) used by the server application */
+var Semaphore = xdc.useModule('ti.sysbios.ipc.Semaphore');
+Semaphore.supportsEvents = true;
+var params = new Semaphore.Params;
+Program.global.semaphore = Semaphore.create(0, params);
+
+if (Program.build.target.name == "M3") {
+ var Cache = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+}
+
+/* *******************************DOMX CHANGES END ******************************* */
+
+/*
+ * ======== CODEC ENGINE configurations ========
+ */
+xdc.useModule('ti.sysbios.ipc.Event');
+xdc.useModule('ti.sysbios.ipc.Mailbox');
+
+var Global = xdc.useModule('ti.sdo.ce.osal.Global');
+//Global.os = xdc.useModule('ti.sdo.ce.osal.bios.Settings');
+Global.runtimeEnv = Global.DSPBIOS;
+
+xdc.useModule('ti.sdo.ce.global.Settings').profile = "debug";
+xdc.loadPackage('ti.sdo.ce.video').profile = "debug";
+xdc.loadPackage('ti.sdo.ce.video3').profile = "debug";
+xdc.loadPackage('ti.sdo.ce.alg').profile = "debug";
+xdc.useModule('ti.sdo.fc.global.Settings').profile = "debug";
+xdc.loadPackage('ti.sdo.fc.rman').profile = "debug";
+xdc.loadPackage('ti.sdo.fc.ires.hdvicp').profile = "debug";
+xdc.loadPackage('ti.sdo.fc.ires.tiledmemory').profile = "debug";
+
+var ipcSettings = xdc.useModule('ti.sdo.ce.ipc.Settings');
+ipcSettings.ipc = xdc.useModule('ti.sdo.ce.ipc.bios.Ipc');
+// set to true to enable debugging of codec engine
+xdc.useModule('ti.sdo.ce.Settings').checked = true;
+
+// Set up gt trace defaults
+var gtinfra = xdc.useModule("ti.sdo.fc.utils.gtinfra.GTINFRA");
+gtinfra.runtimeEnv = gtinfra.NONE;
+var gt = xdc.useModule("ti.sdo.utils.trace.GT");
+gt.MALLOCFXN = "myMalloc";
+gt.PRINTFXN = "printfCaller"
+
+var param1 = new GateMutexPri.Params;
+
+//set All heaps of dskts as the default heap0
+var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');
+DSKT2.DARAM0 = "heap0";
+DSKT2.DARAM1 = "heap0";
+DSKT2.DARAM2 = "heap0";
+DSKT2.SARAM0 = "heap0";
+DSKT2.SARAM1 = "heap0";
+DSKT2.SARAM2 = "heap0";
+DSKT2.ESDATA = "heap0";
+DSKT2.IPROG = "heap0";
+DSKT2.EPROG = "heap0";
+DSKT2.DSKT2_HEAP = "heap0";
+
+
+var HDVICP2 = xdc.useModule('ti.sdo.fc.ires.hdvicp.HDVICP2');
+HDVICP2.memoryBaseAddress[0] = 0xBB000000;
+HDVICP2.registerBaseAddress[0] = 0xBA000000;
+HDVICP2.resetControlAddress[0] = 0xAA306F10;
+HDVICP2.resetFxn = "HDVICP_Reset";
+
+var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');
+//RMAN.common$.gate = GateMutexPri.create(param1);
+
+//
+var HDVICP20API = xdc.useModule('ti.sdo.codecs.hdvicp20api.HDVICP20API');
+
+
+// load whatever codecs are available in the build
+var codecs = [];
+
+function loadCodec(pkg, name)
+{
+ try {
+ var codec = xdc.useModule(pkg);
+ print('loading: ' + name);
+ codecs.push({ name: name, mod: codec, local: true });
+ } catch(e) {
+ print('no package: ' + pkg);
+ }
+}
+
+loadCodec('ti.sdo.codecs.h264dec.ce.H264DEC', 'ivahd_h264dec');
+loadCodec('ti.sdo.codecs.mpeg4dec.ce.MPEG4DEC', 'ivahd_mpeg4dec');
+loadCodec('ti.sdo.codecs.vp6dec.ce.VP6DEC', 'ivahd_vp6dec');
+loadCodec('ti.sdo.codecs.vp7dec.ce.VP7DEC', 'ivahd_vp7dec');
+loadCodec('ti.sdo.codecs.vc1vdec.ce.VC1VDEC', 'ivahd_vc1vdec');
+loadCodec('ti.sdo.codecs.realvdec.ce.REALVDEC', 'ivahd_realvdec');
+loadCodec('ti.sdo.codecs.mpeg2vdec.ce.MPEG2VDEC', 'ivahd_mpeg2vdec');
+
+var engine = xdc.useModule('ti.sdo.ce.Engine');
+var myEngine = engine.create("ivahd_vidsvr", codecs);
+
+//address translation API
+xdc.useModule('ti.omap.mem.SyslinkMemUtils');
+var slpm = xdc.useModule('ti.omap.slpm.slpm');
+
+/*=========Power configuration====*/
+xdc.useModule('ti.sysbios.misc.Queue');
+
+var Timestamp = xdc.useModule("xdc.runtime.Timestamp");
+Timestamp.SupportProxy = xdc.useModule("ti.sysbios.family.arm.ducati.TimestampProvider");
+
+var dmTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+dmTimer.timerSettings[0].baseAddr = 0xA8034000;
+dmTimer.timerSettings[1].baseAddr = 0xA8036000;
+dmTimer.timerSettings[2].baseAddr = 0xA803E000;
+dmTimer.timerSettings[3].baseAddr = 0xA8088000;
+
+var Power = xdc.useModule('ti.sysbios.family.arm.ducati.omap4430.Power');
+Power.loadSegment = "MEM_HEAP_SYSM3";
+Power.sdmaRegs = 0xAA056000;
+
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+Idle.addFunc('&platform_idle_processing');
+/*=========Power configuration====*/
+
View
60 ducati/platform/base_image/package.bld
@@ -0,0 +1,60 @@
+/*
+ * ======== ducati/platform/baseimage/package.bld ========
+ */
+
+var Build = xdc.useModule('xdc.bld.BuildEnvironment');
+var Pkg = xdc.useModule('xdc.bld.PackageContents');
+var compileOpts = " "
+var waval = 0;
+
+var commonBld = xdc.loadCapsule("ducati/build/common.bld");
+
+var SRC_FILES = [
+ "../../../dce.c",
+ "./src/baseimage_ivahd_frwkconfig.c",
+ "./src/iresman_tiledmemory.c",
+ "./src/main.c",
+];
+
+
+coreNames = commonBld.getCores(arguments);
+/* select default as app_m3 */
+if (coreNames.length==0) {
+ coreNames[0] = "app_m3";
+}
+
+var profiles = commonBld.getProfiles(arguments);
+/* If no profiles were assigned, build for release */
+if (profiles.length == 0) {
+ profiles[0] = "whole_program_debug";
+}
+
+for (var i = 0; i < Build.targets.length; i++) {
+
+ var targ = Build.targets[i];
+
+ for (var j = 0; j < coreNames.length; j++) {
+ var coreName = coreNames[j];
+
+ var cfgFileName = 'dce_' + coreName + '.cfg';
+
+ for( var k = 0; k< profiles.length; k++)
+ {
+ var profile = profiles[k];
+ var profileOpts = commonBld.buildOptions(arguments, compileOpts, coreName);
+
+
+ var out_name = 'out/' + coreName + '/' + profile + '/' + 'dce_' + coreName;
+
+ print ("config file: " + cfgFileName + "\n");
+ print ("profile: " + profile + "\n");
+ print(profileOpts+"\r\n");
+ var exe = Pkg.addExecutable(out_name, targ, targ.platform, {cfgScript:cfgFileName, profile:profile, copts: profileOpts, cfgArgs:"{useWa:" +waval+ "}" });
+
+ exe.addObjects(SRC_FILES);
+
+ }
+ }
+}
+
+
View
9 ducati/platform/base_image/package.xdc
@@ -0,0 +1,9 @@
+/*
+ * ======== ducati/platform/base_image/package.xdc ========
+ */
+
+
+/*! Ducati baseimage package. No modules inside */
+package ducati.platform.base_image{
+
+};
View
195 ducati/platform/base_image/src/baseimage_ivahd_frwkconfig.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2010, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <xdc/std.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+#include <ti/sdo/ce/Engine.h>
+#include <ti/sdo/ce/CERuntime.h>
+#include <ti/sdo/utils/trace/gt.h>
+#include <xdc/cfg/global.h>
+
+#include "dce_priv.h"
+
+//#include <ti/omap/mem/shim/MemMgr.h>
+#include <ti/omap/mem/SyslinkMemUtils.h>
+
+#include <ti/xdais/ires.h>
+#include <ti/sdo/fc/ires/hdvicp/iresman_hdvicp.h>
+#include <ti/sdo/fc/ires/hdvicp/ires_hdvicp2.h>
+#include <ti/sdo/fc/ires/tiledmemory/iresman_tiledmemory.h>
+
+
+#define MEMORYSTATS_DEBUG 1
+
+void *MEMUTILS_getPhysicalAddr(Ptr vaddr)
+{
+ unsigned int paddr = SyslinkMemUtils_VirtToPhys(vaddr);
+ DEBUG("virtual addr:%x\tphysical addr:%x", vaddr, paddr);
+ return (void *)paddr;
+}
+
+static Bool allocFxn(IALG_MemRec *memTab, Int numRecs);
+static void freeFxn(IALG_MemRec *memTab, Int numRecs);
+
+
+Void init_IVAHDFrwk(void)
+{
+ IRES_Status ret;
+ IRESMAN_Params rman_params = {
+ .size = sizeof(IRESMAN_Params),
+ .allocFxn = allocFxn,
+ .freeFxn = freeFxn,
+ };
+
+ CERuntime_init();
+
+ ret = RMAN_init();
+ if (ret != IRES_OK) {
+ goto end;
+ }
+
+ /* Register HDVICP with RMAN if not already registered */
+ ret = RMAN_register(&IRESMAN_HDVICP, &rman_params);
+ if ((ret != IRES_OK) && (ret != IRES_EEXISTS)) {
+ DEBUG("could not register IRESMAN_HDVICP: %d", ret);
+ goto end;
+ }
+
+ /* NOTE: this might try MemMgr allocations over RCM remote
+ * call back to host side. Which will fail if we don't
+ * have memsrv. But will eventually fall back to allocFxn
+ * which will allocate from the local heap.
+ */
+ ret = RMAN_register(&IRESMAN_TILEDMEMORY, &rman_params);
+ if ((ret != IRES_OK) && (ret != IRES_EEXISTS)) {
+ DEBUG("could not register IRESMAN_TILEDMEMORY: %d", ret);
+ goto end;
+ }
+
+ DEBUG("RMAN_register() for HDVICP is successful");
+
+end:
+ return;
+}
+
+Void exit_IVAHDFrwk()
+{
+ /* CERuntime_exit() will call global exit that deinitialize all
+ * (RMAN,Algorithm...etc)
+ */
+ DEBUG("call to CERuntime_exit()");
+ CERuntime_exit();
+}
+
+/* we need to track the block size ourselves, to ensure that it is
+ * properly deallocated
+ */
+typedef struct {
+ Uns size;
+ void *ptr;
+} MemHeader;
+
+#define P2H(p) (&(((MemHeader *)(p))[-1]))
+
+static Bool allocFxn(IALG_MemRec memTab[], Int n)
+{
+ Int i;
+#ifdef MEMORYSTATS_DEBUG
+ Memory_Stats stats;
+#endif
+
+ for (i = 0; i < n; i++) {
+ Error_Block eb;
+ Uns pad, size;
+ void *blk;
+ MemHeader *hdr;
+
+ if (memTab[i].alignment > sizeof(MemHeader)) {
+ pad = memTab[i].alignment;
+ } else {
+ pad = sizeof(MemHeader);
+ }
+
+ size = memTab[i].size + pad;
+
+#ifdef MEMORYSTATS_DEBUG
+ Memory_getStats(heap1, &stats);
+ INFO("Total: %d\tFree: %d\tLargest: %d", stats.totalSize,
+ stats.totalFreeSize, stats.largestFreeSize);
+#endif
+
+ blk = Memory_alloc(heap1, size, memTab[i].alignment, &eb);
+
+ if (!blk) {
+ ERROR("MemTab Allocation failed at %d", i);
+ freeFxn(memTab, i);
+ return FALSE;
+ } else {
+ memTab[i].base = (void *)((char *)blk + pad);
+ hdr = P2H(memTab[i].base);
+ hdr->size = size;
+ hdr->ptr = blk;
+ DEBUG("%d: alloc: %p/%p (%d)", i, hdr->ptr,
+ memTab[i].base, hdr->size);
+ }
+ }
+ DEBUG("MemTab Allocation is Successful");
+ return TRUE;
+}
+
+static void freeFxn(IALG_MemRec memTab[], Int n)
+{
+ Int i;
+#ifdef MEMORYSTATS_DEBUG
+ Memory_Stats stats;
+#endif
+
+ for (i = 0; i < n; i++) {
+ if (memTab[i].base != NULL) {
+ MemHeader *hdr = P2H(memTab[i].base);
+
+#ifdef MEMORYSTATS_DEBUG
+ DEBUG("%d: free: %p/%p (%d)", n, hdr->ptr,
+ memTab[i].base, hdr->size);
+#endif
+ Memory_free(heap1, hdr->ptr, hdr->size);
+ }
+#ifdef MEMORYSTATS_DEBUG
+ Memory_getStats(heap1, &stats);
+ INFO("Total: %d\tFree: %d\tLargest: %d", stats.totalSize,
+ stats.totalFreeSize, stats.largestFreeSize);
+#endif
+ }
+}
View
184 ducati/platform/base_image/src/iresman_tiledmemory.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2011, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* This is a dummy implementation of "ti.sdo.fc.ires.tiledmemory"
+ * that just allocates from the heap:
+ */
+
+#include <xdc/std.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Assert.h>
+//#include <xdc/runtime/Diags.h>
+//#include <xdc/runtime/Log.h>
+//#include <xdc/runtime/Registry.h>
+
+//#include <ti/xdais/xdas.h>
+//#include <ti/xdais/ires_common.h>
+#include <ti/xdais/ires.h>
+
+#include <ti/sdo/fc/ires/iresman.h>
+#include <ti/sdo/fc/ires/tiledmemory/ires_tiledmemory.h>
+
+#include "dce_priv.h"
+
+
+static IRESMAN_PersistentAllocFxn * allocFxn; /* Memory alloc function */
+static IRESMAN_PersistentFreeFxn * freeFxn; /* Memory free function */
+
+static void * allocRes(int size)
+{
+ IALG_MemRec rec = {
+ .size = size,
+ .alignment = 0x4,
+ .space = IALG_EXTERNAL,
+ .attrs = IALG_PERSIST,
+ };
+ if (! allocFxn(&rec, 1)) {
+ return NULL;
+ }
+ return rec.base;
+}
+
+static void freeRes(void *base, int size)
+{
+ IALG_MemRec rec = {
+ .base = base,
+ .size = size,
+ .alignment = 0x4,
+ .space = IALG_EXTERNAL,
+ .attrs = IALG_PERSIST,
+ };
+
+ freeFxn(&rec, 1);
+}
+
+static String getProtocolName()
+{
+ return "ti.sdo.fc.ires.tiledmemory";
+}
+
+static IRES_ProtocolRevision * getProtocolRevision()
+{
+ static IRES_ProtocolRevision revision = {1, 0, 0};
+ return &revision;
+}
+
+static IRES_Status init(IRESMAN_Params * initArgs)
+{
+ allocFxn = initArgs->allocFxn;
+ freeFxn = initArgs->freeFxn;
+ return IRES_OK;
+}
+
+static IRES_Status exit()
+{
+ return IRES_OK;
+}
+
+static void getStaticProperties(IRES_Handle resourceHandle,
+ IRES_Properties * resourceProperties)
+{
+ /* unused */
+}
+
+static IRES_Handle getHandles(IALG_Handle algHandle,
+ IRES_ResourceDescriptor *resDesc, Int scratchGroupId,
+ IRES_Status *status)
+{
+ IRES_TILEDMEMORY_ProtocolArgs *args =
+ (IRES_TILEDMEMORY_ProtocolArgs *)resDesc->protocolArgs;
+ IRES_TILEDMEMORY_Handle handle = NULL;
+ Void *ptr = NULL;
+
+ Assert_isTrue(args, NULL);
+ Assert_isTrue(algHandle, NULL);
+
+ ptr = allocRes(args->sizeDim0 * args->sizeDim1);
+ if (!ptr) {
+ ERROR("could not allocate buffer: %dx%d",
+ args->sizeDim0, args->sizeDim1);
+ goto fail;
+ }
+
+ handle = allocRes(sizeof(*handle));
+ if (!handle) {
+ ERROR("could not allocate handle");
+ goto fail;
+ }
+
+ handle->ires.getStaticProperties = getStaticProperties;
+ handle->ires.persistent = IRES_PERSISTENT;
+ handle->memoryBaseAddress = ptr; /* MMU set up for 0x0 offset */
+ handle->systemSpaceBaseAddress = ptr;
+ handle->isTiledMemory = FALSE;
+ handle->accessUnit = IRES_TILEDMEMORY_RAW;
+ handle->tilerBaseAddress = NULL;
+
+ DEBUG("allocation succeeded: %dx%d", args->sizeDim0, args->sizeDim1);
+
+ return (IRES_Handle)handle;
+
+fail:
+ if (ptr) freeRes(ptr, args->sizeDim0 * args->sizeDim1);
+ if (handle) freeRes(handle, sizeof(*handle));
+ return NULL;
+}
+
+static IRES_Status freeHandles(IALG_Handle algHandle,
+ IRES_Handle algResourceHandle,
+ IRES_ResourceDescriptor *resDesc,
+ Int scratchGroupId)
+{
+ IRES_TILEDMEMORY_ProtocolArgs *args =
+ (IRES_TILEDMEMORY_ProtocolArgs *)resDesc->protocolArgs;
+ IRES_TILEDMEMORY_Handle handle =
+ (IRES_TILEDMEMORY_Handle)algResourceHandle;
+
+ Assert_isTrue(args, NULL);
+ Assert_isTrue(handle, NULL);
+
+ freeRes(handle->memoryBaseAddress, args->sizeDim0 * args->sizeDim1);
+ freeRes(handle, sizeof(*handle));
+
+ return IRES_OK;
+}
+
+
+IRESMAN_Fxns IRESMAN_TILEDMEMORY = {
+ getProtocolName,
+ getProtocolRevision,
+ init,
+ exit,
+ getHandles,
+ freeHandles,
+};
View
332 ducati/platform/base_image/src/main.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2010, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <xdc/std.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/IHeap.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/ipc/Semaphore.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/hal/ammu/AMMU.h>
+#include <ti/sysbios/family/arm/ducati/CTM.h>
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/omap/slpm/idle.h>
+#include <ti/omap/mem/shim/MemMgr.h>
+#include <ti/sysbios/hal/Timer.h>
+#include <ti/sysbios/heaps/HeapMem.h>
+
+#include <ti/sysbios/family/arm/ducati/GateDualCore.h>
+
+
+#include <ti/ipc/Ipc.h>
+#include <ti/ipc/MultiProc.h>
+#include <ti/sdo/utils/MultiProc.h>
+#include <xdc/runtime/Diags.h>
+#include <ti/sdo/fc/global/FCSettings.h>
+#include <ti/sdo/ce/global/CESettings.h>
+
+#include "dce_priv.h"
+
+#define PM_IVAHD_PWRSTCTRL (*(volatile unsigned int *)0xAA306F00)
+#define RM_IVAHD_RSTCTRL (*(volatile unsigned int *)0xAA306F10)
+#define RM_IVAHD_RSTST (*(volatile unsigned int *)0xAA306F14)
+
+#define CM_IVAHD_CLKSTCTRL (*(volatile unsigned int *)0xAA008F00)
+#define CM_IVAHD_CLKCTRL (*(volatile unsigned int *)0xAA008F20)
+#define CM_IVAHD_SL2_CLKCTRL (*(volatile unsigned int *)0xAA008F28)
+
+#define CM_DIV_M5_DPLL_IVA (*(volatile unsigned int *)0xAA0041BC)
+
+#define IVAHD_CONFIG_REG_BASE (0xBA000000)
+#define ICONT1_ITCM_BASE (IVAHD_CONFIG_REG_BASE + 0x08000)
+#define ICONT2_ITCM_BASE (IVAHD_CONFIG_REG_BASE + 0x18000)
+
+
+
+/*******************************************************************************
+ * Hex code to set for Stack setting, Interrupt vector setting
+ * and instruction to put ICONT in WFI mode.
+ * This shall be placed at TCM_BASE_ADDRESS of given IVAHD, which is
+ * 0x0000 locally after reset.
+ *******************************************************************************/
+
+const unsigned int icont_boot[] = {
+ 0xEA000006,
+ 0xEAFFFFFE,
+ 0xEAFFFFFE,
+ 0xEAFFFFFE,
+ 0xEAFFFFFE,
+ 0xEAFFFFFE,
+ 0xEAFFFFFE,
+ 0xEAFFFFFE,
+ 0xE3A00000,
+ 0xEE070F9A,
+ 0xEE070F90,
+ 0xE3A00000,
+ 0xEAFFFFFE,
+ 0xEAFFFFF1
+};
+
+UInt32 HDVICP_Reset(void * handle, void * iresHandle)
+{
+ int i;
+ volatile unsigned int *icont1_itcm_base_addr =
+ (unsigned int *)ICONT1_ITCM_BASE;
+ volatile unsigned int *icont2_itcm_base_addr =
+ (unsigned int *)ICONT2_ITCM_BASE;
+
+ /*
+ * Reset IVA HD, SL2 and ICONTs
+ */
+
+ DEBUG("HDVICP_Reset");
+
+ /* First put IVA into HW Auto mode */
+ CM_IVAHD_CLKSTCTRL |= 0x00000003;
+
+ /* Wait for IVA HD to standby */
+ while (!((CM_IVAHD_CLKCTRL) & 0x00040000));
+
+ /* Disable IVAHD and SL2 modules */
+ CM_IVAHD_CLKCTRL = 0x00000000;
+ CM_IVAHD_SL2_CLKCTRL = 0x00000000;
+
+ /* Ensure that IVAHD and SL2 are disabled */
+ while (!(CM_IVAHD_CLKCTRL & 0x00030000));
+ while (!(CM_IVAHD_SL2_CLKCTRL & 0x00030000));
+
+ /* Reset IVAHD sequencers and SL2 */
+ RM_IVAHD_RSTCTRL |= 0x00000007;
+
+ /*
+ * Check if modules are reset
+ */
+
+ /* First clear the status bits */
+ RM_IVAHD_RSTST |= 0x00000007;
+
+ /* Wait for confirmation that the systems have been reset */
+ /* THIS CHECK MAY NOT BE NECESSARY, AND MOST OF ALL GIVEN OUR STATE,
+ * MAY NOT BE POSSIBLE
+ */
+
+ /* Copy boot code to ICONT1 & ICONT2 memory */
+ for (i = 0; i < DIM(icont_boot); i++) {
+ *icont1_itcm_base_addr++ = icont_boot[i];
+ *icont2_itcm_base_addr++ = icont_boot[i];
+ }
+
+ /* Ensure that the wake up mode is set to SW_WAKEUP */
+ CM_IVAHD_CLKSTCTRL &= 0x00000002;
+
+ /* Enable IVAHD and SL2 modules */
+ CM_IVAHD_CLKCTRL = 0x00000001;
+ CM_IVAHD_SL2_CLKCTRL = 0x00000001;
+
+ /* Deassert the SL2 reset */
+ RM_IVAHD_RSTCTRL &= 0xFFFFFFFB;
+
+ /* Ensure that IVAHD and SL2 are enabled */
+ while (CM_IVAHD_CLKCTRL & 0x00030000);
+ while (CM_IVAHD_SL2_CLKCTRL & 0x00030000);
+
+ return TRUE;
+}
+
+static int ivahd_use_cnt = 0;
+
+static inline void set_ivahd_opp(int opp)
+{
+ unsigned int val;
+
+ switch (opp) {
+ case 0: val = 0x010e; break;
+ case 50: val = 0x000e; break;
+ case 100: val = 0x0007; break;
+ default: ERROR("invalid opp"); return;
+ }
+
+ DEBUG("CM_DIV_M5_DPLL_IVA=%08x", CM_DIV_M5_DPLL_IVA);
+ /* set HSDIVDER_CLKOUT2_DIV */
+ CM_DIV_M5_DPLL_IVA = (CM_DIV_M5_DPLL_IVA & ~0x0000011f) | val;
+ DEBUG("CM_DIV_M5_DPLL_IVA=%08x", CM_DIV_M5_DPLL_IVA);
+}
+
+void ivahd_acquire(void)
+{
+ UInt hwiKey = Hwi_disable();
+ if (++ivahd_use_cnt == 1) {
+ DEBUG("ivahd acquire");
+ set_ivahd_opp(100);
+ } else {
+ DEBUG("ivahd already acquired");
+ }
+ Hwi_restore(hwiKey);
+}
+
+void ivahd_release(void)
+{
+ UInt hwiKey = Hwi_disable();
+ if (ivahd_use_cnt-- == 1) {
+ DEBUG("ivahd release");
+ set_ivahd_opp(0);
+ } else {
+ DEBUG("ivahd still in use");
+ }
+ Hwi_restore(hwiKey);
+}
+
+#define REG32(A) (*(volatile UInt32 *) (A))
+
+void platform_idle_processing()
+{
+ /* wrapper slpm_idle_processing to ensure all necessary wakeup events
+ * are enabled
+ */
+ REG32(WUGEN_MEVT0) |= (WUGEN_IVAHD_MAILBOX_IRQ_2 | WUGEN_IVAHD_IRQ2 | WUGEN_IVAHD_IRQ1);
+ slpm_idle_processing();
+}
+
+
+void platform_init()
+{
+ Int status = 0;
+ UInt16 hostId = 0, sysProcId = 0;
+
+ /* clear HSDIVDER_CLKOUT2_DIV */
+ set_ivahd_opp(0);
+
+ /* Set up interprocessor notifications */
+ DEBUG("Setting up IPC");
+ status = Ipc_start();
+ if (status < 0) {
+ ERROR("Ipc_start failed: %08x", status);
+ return;
+ }
+
+ /* attach to host */
+ hostId = MultiProc_getId("MPU");
+ DEBUG("APPM3: IPC attaching to MPU, hostId = %d", hostId);
+ do {
+ status = Ipc_attach(hostId);
+ DEBUG("APPM3: IPC attaching... %08x", status);
+ } while (status < 0);
+
+ /* attach to other M3.. do we need this? */
+ sysProcId = MultiProc_getId("SysM3");
+ DEBUG("APPM3: IPC attaching to SysM3, sysProcId = %d", sysProcId);
+
+ do {
+ status = Ipc_attach(sysProcId);
+ DEBUG("APPM3: IPC attaching... %08x", status);
+ } while (status < 0);
+
+ /* maybe above stuff should move into dce_init().. */
+ dce_init();
+ DEBUG("APPM3: Completed IPC setup and Server Bringup");
+
+ return;
+}
+
+
+void platform_deinit()
+{
+ DEBUG("APPM3: Shutdown");
+ dce_deinit();
+}
+
+
+
+unsigned int ducatiSysClock;
+
+extern Void init_IVAHDFrwk();
+extern Void exit_IVAHDFrwk();
+
+Void Ducati_AppTask (UArg arg1, UArg arg2)
+{
+ FCSettings_init();
+ Diags_setMask(FCSETTINGS_MODNAME"+12345678LEXAIZFS");
+ CESettings_init();
+ Diags_setMask(CESETTINGS_MODNAME"+12345678LEXAIZFS");
+// Diags_setMask("ti.sdo.rcm.RcmServer-12");
+// Diags_setMask("ti.sysbios.utils.Load-4");
+
+ init_IVAHDFrwk();
+ HDVICP_Reset(NULL, NULL);
+ platform_init();
+
+ /* how do we know when to unload.. */
+ while (1) {
+ Task_sleep(0x7fffffff);
+ }
+
+ /*The test cases will run in this task's context in the init call.
+ Once init returns, testcases have exited so do deinit*/
+ platform_deinit();
+
+ exit_IVAHDFrwk();
+
+ System_exit(0);
+}
+
+/*
+ * === FUNCTION ======================================================================
+ * Name: main
+ * Description: Main entry for Ducati subsystem
+ * =====================================================================================
+ */
+
+
+int main(void)
+{
+#if defined(DUCATI_APP_M3)
+ /* Hack to enable CMT for APP M3 */
+ if ((CTM_ctm.CTGNBL[0] && 0x14) != 0x14) {
+ CTM_ctm.CTCNTL |= 1; /* enable the CTM */
+
+ CTM_ctm.CTCR[2] = 0x4; /* enable Chain mode, count cycles */
+ CTM_ctm.CTCR[3] = 0x4; /* enable Chain mode, count cycles */
+ CTM_ctm.CTCR[4] = 0x4; /* enable Chain mode, count cycles */
+ CTM_ctm.CTCR[5] = 0x4; /* enable Chain mode, count cycles */
+
+ CTM_ctm.CTGRST[0] |= 0x3c; /* reset counters 2,3,4,5 syncronously */
+ CTM_ctm.CTGNBL[0] |= 0x14; /* enable counters 2,4 syncronously */
+ }
+#endif
+
+ BIOS_start();
+}
+
View
456 memsrv.c
@@ -1,456 +0,0 @@
-/*
- * Copyright (c) 2010, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* NOTE: this code should be folded into a library as part of syslink.. but
- * for now, this ugly hack of duplicating code from syslink and domx..
- */
-
-/*============================================================================
- * @file MemMgr.c
- *
- * @brief TILER Client Sample application for TILER module between MPU & Ducati
- *
- * ============================================================================
- */
-
-
-/* OS-specific headers */
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <stdint.h>
-
-#include <pthread.h>
-#include <semaphore.h>
-#include <signal.h>
-
-/* Standard headers */
-#include <Std.h>
-
-/* OSAL & Utils headers */
-#include <OsalPrint.h>
-#include <String.h>
-#include <Trace.h>
-
-/* IPC headers */
-#include <IpcUsr.h>
-#include <ProcMgr.h>
-
-/* RCM headers */
-#include <RcmServer.h>
-
-/* TILER headers */
-#include <tilermgr.h>
-
-#if defined (__cplusplus)
-extern "C" {
-#endif /* defined (__cplusplus) */
-
-/** ============================================================================
- * Macros and types
- * ============================================================================
- */
-
-#define DIM(x) (sizeof (x) / sizeof((x)[0]))
-
-static RcmServer_Handle rcmServerHandle;
-
-
-/*
- * Remote function argument structures
- *
- * All fields are simple UInts and Ptrs. Some arguments may be smaller than
- * these fields, which is okay, as long as they are correctly "unpacked" by the
- * server.
- */
-
-typedef struct {
- UInt pixelFormat;
- UInt width;
- UInt height;
- UInt length;
- UInt stride;
- Ptr ptr;
- UInt * reserved;
-} AllocParams;
-
-typedef struct {
- UInt numBuffers;
- AllocParams params [1];
-} AllocArgs;
-
-typedef struct {
- Ptr bufPtr;
-} FreeArgs, ConvertPageModeToTilerSpaceArgs;
-
-typedef struct {
- Ptr bufPtr;
- UInt rotationAndMirroring;
-} ConvertToTilerSpaceArgs;
-
-typedef struct {
- UInt32 code;
-} DebugArgs;
-
-
-typedef struct { /* TODO: remove */
- enum pixel_fmt_t pixelFormat; /* pixel format */
- union {
- struct {
- pixels_t width; /* width of 2D buffer */
- pixels_t height; /* height of 2D buffer */
- };
- struct {
- bytes_t length; /* length of 1D buffer. Must be multiple of
- stride if stride is not 0. */
- };
- };
- unsigned long stride; /* must be multiple of page size. Can be 0 only
- if pixelFormat is KPAGE. */
- void * ptr; /* pointer to beginning of buffer */
- unsigned long reserved; /* system space address (used internally) */
-} MemMgrBlock;
-
-/*
- * ======== getAccessMode ========
- * helper func to determine bit mode
- */
-static
-UInt getAccessMode (Ptr bufPtr)
-{
- UInt addr = (UInt)bufPtr;
-
- /*
- * The access mode decoding is as follows:
- *
- * 0x60000000 - 0x67FFFFFF : 8-bit
- * 0x68000000 - 0x6FFFFFFF : 16-bit
- * 0x70000000 - 0x77FFFFFF : 32-bit
- * 0x77000000 - 0x7FFFFFFF : Page mode
- */
- switch (addr & 0xf8000000) { /* Mask out the lower bits */
- case 0x60000000:
- return PIXEL_FMT_8BIT;
- case 0x68000000:
- return PIXEL_FMT_16BIT;
- case 0x70000000:
- return PIXEL_FMT_32BIT;
- case 0x78000000:
- return PIXEL_FMT_PAGE;
- default: /* TODO: How to handle invalid case? */
- return 0;
- }
-}
-
-/*
- * ======== getStride ========
- * helper func to determine stride length
- */
-static
-UInt getStride (Ptr bufPtr)
-{
- switch (getAccessMode (bufPtr)) {
- case PIXEL_FMT_8BIT:
- return 0x4000; /* 16 KB of stride */
- case PIXEL_FMT_16BIT:
- case PIXEL_FMT_32BIT:
- return 0x8000; /* 32 KB of stride */
- default:
- return 0; /* Stride not applicable */
- }
-}
-
-/*
- * ======== fxnMemMgr_Debug ========
- * RCM function for debugging
-*/
-static
-Int32 fxnMemMgr_Debug (UInt32 dataSize, UInt32 *data)
-{
- DebugArgs * args = (DebugArgs *)data;
- Osal_printf ("Executing MemMgr_Debug: %08x\n", args->code);
-}
-
-/*
- * ======== fxnMemMgr_Alloc ========
- * RCM function for MemMgr_Alloc function
-*/
-static
-Int32 fxnMemMgr_Alloc (UInt32 dataSize, UInt32 *data)
-{
- AllocArgs * args = (AllocArgs *)data;
- Int i;
- MemMgrBlock * params;
- Ptr allocedPtr;
-
- Osal_printf ("Executing MemMgr_Alloc with params:\n");
- Osal_printf ("\tnumBuffers = %d\n", args->numBuffers);
- for(i = 0; i < args->numBuffers; i++) {
- Osal_printf ("\tparams [%d].pixelFormat = %d\n", i,
- args->params [i].pixelFormat);
- Osal_printf ("\tparams [%d].width = %d\n", i, args->params [i].width);
- Osal_printf ("\tparams [%d].height = %d\n", i, args->params [i].height);
- Osal_printf ("\tparams [%d].length = %d\n", i, args->params [i].length);
- }
-
- params = (MemMgrBlock *) malloc (sizeof(MemMgrBlock) * args->numBuffers);
-
- if (params == NULL) {
- Osal_printf ("Error allocating array of MemMgrBlock params.\n");
- return (Int32)NULL;
- }
-
- for(i = 0; i < args->numBuffers; i++) {
- params [i].pixelFormat = args->params [i].pixelFormat;
-
- params [i].width = args->params [i].width;
- /* TODO: provide length support on Ducati */
- params [i].height = args->params [i].height;
- params [i].length = args->params [i].length;
- }
-
- /* Allocation */
- for (i = 0; i < args->numBuffers; i++) {
- switch (params [i].pixelFormat) {
- case PIXEL_FMT_8BIT:
- case PIXEL_FMT_16BIT:
- case PIXEL_FMT_32BIT:
- Osal_printf ("fxnMemMgr_Alloc: calling TilerMgr_Alloc.\n");
- args->params [i].ptr = (Ptr)TilerMgr_Alloc (params [i].pixelFormat,
- params [i].width, params [i].height);
- break;
- case PIXEL_FMT_PAGE:
- Osal_printf ("fxnMemMgr_Alloc: calling TilerMgr_PageModeAlloc.\n");
- args->params [i].ptr = \
- (Ptr)TilerMgr_PageModeAlloc (params [i].length);
- break;
- default: /* Invalid case */
- Osal_printf ("fxnMemMgr_Alloc: Invalid pixel format.\n");
- args->params [i].ptr = NULL;
- break;
- }
- args->params [i].stride = getStride (args->params [i].ptr);
- }
-
- allocedPtr = args->params [0].ptr;
- free (params);
-
- Osal_printf ("fxnMemMgr_Alloc done.\n");
- return (Int32) allocedPtr; /* Return first buffer pointer */
-}
-
-
-
-/*
- * ======== fxnMemMgr_Free ========
- * RCM function for MemMgr_Free
- */
-static
-Int32 fxnMemMgr_Free (UInt32 dataSize, UInt32 *data)
-{
- FreeArgs * args = (FreeArgs *)data;
- UInt32 status = 0;
-
- Osal_printf ("Executing MemMgr_Free with params:\n");
- Osal_printf ("\tbufPtr = 0x%x\n", args->bufPtr);
-
- switch (getAccessMode (args->bufPtr)) {
- case PIXEL_FMT_8BIT:
- case PIXEL_FMT_16BIT:
- case PIXEL_FMT_32BIT:
- Osal_printf ("fxnMemAlloc_Free: calling TilerMgr_Free.\n");
- status = TilerMgr_Free ((Int)args->bufPtr);
- break;
- case PIXEL_FMT_PAGE:
- Osal_printf ("fxnMemAlloc_Free: calling TilerMgr_PageModeFree.\n");
- status = TilerMgr_PageModeFree ((Int)args->bufPtr);
- break;
- default: /* Invalid case */
- Osal_printf ("fxnMemAlloc_Free: Invalid pointer.\n");
- break;
- }
-
- Osal_printf ("fxnMemMgr_Free done.\n");
- return status;
-}
-
-/*
- * ======== fxnTilerMem_ConvertToTilerSpace ========
- * RCM function for TilerMem_ConvertToTilerSpace
- */
-static
-Int32 fxnTilerMem_ConvertToTilerSpace (UInt32 dataSize, UInt32 *data)
-{
- ConvertToTilerSpaceArgs * args = (ConvertToTilerSpaceArgs *)data;
- UInt32 addr;
-
- Osal_printf ("Executing TilerMem_ConvertToTilerSpace with params:\n");
- Osal_printf ("\tbufPtr = 0x%x\n", args->bufPtr);
- Osal_printf ("\trotationAndMirroring = 0x%x\n", args->rotationAndMirroring);
-
- //Stubbed out pending implementation
- /*addr = TilerMem_ConvertToTilerSpace (args->bufPtr,
- args->rotationAndMirroring);*/
- addr = TRUE;
-
- return addr;
-}
-
-/*
- * ======== fxnTilerMem_ConvertPageModeToTilerSpace ========
- * RCM function for TilerMem_ConvertPageModeToTilerSpace
- */
-static
-Int32 fxnTilerMem_ConvertPageModeToTilerSpace (UInt32 dataSize, UInt32 *data)
-{
- ConvertPageModeToTilerSpaceArgs * args = \
- (ConvertPageModeToTilerSpaceArgs *)data;
- UInt32 addr;
-
- Osal_printf ("Executing TilerMem_ConvertPageModeToTilerSpace with params:");
- Osal_printf ("\n\tbufPtr = 0x%x\n", args->bufPtr);
-
- //Stubbed out pending implementation
- //addr = TilerMem_ConvertPageModeToTilerSpace (args->bufPtr);
- addr = TRUE;
-
- return addr;
-}
-
-struct MemMgr_funcInfo {
- RcmServer_MsgFxn fxnPtr;
- String name;
-};
-
-static struct MemMgr_funcInfo memMgrFxns [] =
-{
- { fxnMemMgr_Alloc, "MemMgr_Alloc"},
- { fxnMemMgr_Free, "MemMgr_Free"},
- { fxnMemMgr_Debug, "MemMgr_Debug"},
- { fxnTilerMem_ConvertToTilerSpace, "TilerMem_ConvertToTilerSpace"},
- { fxnTilerMem_ConvertPageModeToTilerSpace,
- "TilerMem_ConvertPageModeToTilerSpace"},
-};
-
-/*
- * ======== MemMgrThreadFxn ========
- * TILER server thread function
- */
-
-int
-memsrv_init (char *name)
-{
- Int status;
- RcmServer_Params rcmServerParams;
- UInt fxnIdx;
- Int i;
-
- /* RCM Server module init */
- Osal_printf ("RCM Server module init.\n");
- RcmServer_init ();
-
- /* rcm client module params init*/
- Osal_printf ("RCM Server module params init.\n");
- status = RcmServer_Params_init (&rcmServerParams);
- if (status < 0) {
- Osal_printf ("Error in RCM Server instance params init \n");
- return status;
- }
-
- /* create the RcmServer instance */
- Osal_printf ("Creating RcmServer instance: %s\n", name);
- status = RcmServer_create (name, &rcmServerParams,
- &rcmServerHandle);
- if (status < 0) {
- Osal_printf ("Error in RCM Server create.\n");
- return status;
- }
-
- for (i = 0; i < DIM (memMgrFxns); i++) {
- status = RcmServer_addSymbol (rcmServerHandle, memMgrFxns [i].name,
- memMgrFxns [i].fxnPtr, &fxnIdx);
- /* Register the remote functions */
- Osal_printf ("Registering remote function %s with index %d\n",
- memMgrFxns [i].name, fxnIdx);
- if (status < 0) {
- Osal_printf ("Add symbol failed with status 0x%08x.\n", status);
- return status;
- }
- }
-
- status = TilerMgr_Open ();
- if (status < 0) {
- Osal_printf ("Error in TilerMgr_Open: status = 0x%x\n", status);
- return status;
- }
-
- Osal_printf ("Start RCM server thread \n");
- RcmServer_start (rcmServerHandle);
-
- Osal_printf ("\nDone initializing RCM server. Ready to receive requests "
- "from Ducati.\n");
-
- return status;
-}
-
-int
-memsrv_deinit (void)
-{
- Int status;
- Int i;
-
- if (! rcmServerHandle) {
- return 0;
- }
-
- for (i = 0; i < DIM (memMgrFxns); i++) {
- /* Unregister the remote functions */
- status = RcmServer_removeSymbol (rcmServerHandle, memMgrFxns [i].name);
- if (status < 0) {
- Osal_printf ("Remove symbol %s failed.\n", memMgrFxns [i].name);
- }
- }
-
- status = RcmServer_delete (&rcmServerHandle);
- if (status < 0) {
- Osal_printf ("Error in RcmServer_delete: status = 0x%x\n", status);
- return status;
- }
-
- RcmServer_exit ();
-
- return 0;
-}
-
-#if defined (__cplusplus)
-}
-#endif /* defined (__cplusplus) */
View
283 packages/ivahd_codecs/ti/sdo/codecs/h264dec/ih264vdec.h
@@ -1,121 +1,162 @@
-/*
- * Copyright (c) 2010, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef __IH264VDEC_H__
-#defi