diff --git a/Board/ems11-bb37/Clock_50to100Split.asy b/Board/ems11-bb37/Clock_50to100Split.asy new file mode 100644 index 0000000..6fc180a --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 Clock_50to100Split +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk_in1 +PINATTR Polarity IN +LINE Normal 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 176 576 176 +PIN 608 176 RIGHT 36 +PINATTR PinName clk_out2 +PINATTR Polarity OUT +LINE Normal 608 272 576 272 +PIN 608 272 RIGHT 36 +PINATTR PinName clk_out3 +PINATTR Polarity OUT +LINE Normal 608 976 576 976 +PIN 608 976 RIGHT 36 +PINATTR PinName locked +PINATTR Polarity OUT + diff --git a/Board/ems11-bb37/Clock_50to100Split.gise b/Board/ems11-bb37/Clock_50to100Split.gise new file mode 100644 index 0000000..d53b31d --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.gise @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + diff --git a/Board/ems11-bb37/Clock_50to100Split.ncf b/Board/ems11-bb37/Clock_50to100Split.ncf new file mode 100644 index 0000000..fbd7be2 --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.ncf @@ -0,0 +1,60 @@ +# file: Clock_50to100Split.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints +PIN "RESET" TIG; + + diff --git a/Board/ems11-bb37/Clock_50to100Split.sym b/Board/ems11-bb37/Clock_50to100Split.sym new file mode 100644 index 0000000..dbff1c6 --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.sym @@ -0,0 +1,27 @@ + + + BLOCK + 2014-8-14T16:49:25 + + + + + + + + Clock_50to100Split + + + + + + + + + + + + + + + diff --git a/Board/ems11-bb37/Clock_50to100Split.ucf b/Board/ems11-bb37/Clock_50to100Split.ucf new file mode 100644 index 0000000..fac6887 --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.ucf @@ -0,0 +1,59 @@ +# file: Clock_50to100Split.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints +PIN "RESET" TIG; + diff --git a/Board/ems11-bb37/Clock_50to100Split.vhd b/Board/ems11-bb37/Clock_50to100Split.vhd new file mode 100644 index 0000000..1696089 --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.vhd @@ -0,0 +1,178 @@ +-- file: Clock_50to100Split.vhd +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------ +-- User entered comments +------------------------------------------------------------------------------ +-- None +-- +------------------------------------------------------------------------------ +-- "Output Output Phase Duty Pk-to-Pk Phase" +-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +------------------------------------------------------------------------------ +-- CLK_OUT1___100.000______0.000______50.0______233.202____213.839 +-- CLK_OUT2___100.000_____30.000______50.0______233.202____213.839 +-- CLK_OUT3____25.000______0.000______50.0______311.133____213.839 +-- +------------------------------------------------------------------------------ +-- "Input Clock Freq (MHz) Input Jitter (UI)" +------------------------------------------------------------------------------ +-- __primary__________50.000____________0.010 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +entity Clock_50to100Split is +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Clock out ports + CLK_OUT1 : out std_logic; + CLK_OUT2 : out std_logic; + CLK_OUT3 : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end Clock_50to100Split; + +architecture xilinx of Clock_50to100Split is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of xilinx : architecture is "Clock_50to100Split,clk_wiz_v3_6,{component_name=Clock_50to100Split,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; + -- Input clock buffering / unused connectors + signal clkin1 : std_logic; + -- Output clock buffering / unused connectors + signal clkfbout : std_logic; + signal clkout0 : std_logic; + signal clkout1 : std_logic; + signal clkout2 : std_logic; + signal clkout3_unused : std_logic; + signal clkout4_unused : std_logic; + signal clkout5_unused : std_logic; + -- Unused status signals + +begin + + + -- Input buffering + -------------------------------------- + clkin1_buf : IBUFG + port map + (O => clkin1, + I => CLK_IN1); + + + -- Clocking primitive + -------------------------------------- + -- Instantiation of the PLL primitive + -- * Unused inputs are tied off + -- * Unused outputs are labeled unused + + pll_base_inst : PLL_BASE + generic map + (BANDWIDTH => "OPTIMIZED", + CLK_FEEDBACK => "CLKFBOUT", + COMPENSATION => "INTERNAL", + DIVCLK_DIVIDE => 1, + CLKFBOUT_MULT => 12, + CLKFBOUT_PHASE => 0.000, + CLKOUT0_DIVIDE => 6, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT1_DIVIDE => 6, + CLKOUT1_PHASE => 30.000, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT2_DIVIDE => 24, + CLKOUT2_PHASE => 0.000, + CLKOUT2_DUTY_CYCLE => 0.500, + CLKIN_PERIOD => 20.000, + REF_JITTER => 0.010) + port map + -- Output clocks + (CLKFBOUT => clkfbout, + CLKOUT0 => clkout0, + CLKOUT1 => clkout1, + CLKOUT2 => clkout2, + CLKOUT3 => clkout3_unused, + CLKOUT4 => clkout4_unused, + CLKOUT5 => clkout5_unused, + -- Status and control signals + LOCKED => LOCKED, + RST => RESET, + -- Input clock control + CLKFBIN => clkfbout, + CLKIN => clkin1); + + -- Output buffering + ------------------------------------- + + + clkout1_buf : BUFG + port map + (O => CLK_OUT1, + I => clkout0); + + + + clkout2_buf : BUFG + port map + (O => CLK_OUT2, + I => clkout1); + + clkout3_buf : BUFG + port map + (O => CLK_OUT3, + I => clkout2); + +end xilinx; diff --git a/Board/ems11-bb37/Clock_50to100Split.vho b/Board/ems11-bb37/Clock_50to100Split.vho new file mode 100644 index 0000000..23e2384 --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.vho @@ -0,0 +1,98 @@ +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------ +-- User entered comments +------------------------------------------------------------------------------ +-- None +-- +------------------------------------------------------------------------------ +-- "Output Output Phase Duty Pk-to-Pk Phase" +-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +------------------------------------------------------------------------------ +-- CLK_OUT1___100.000______0.000______50.0______233.202____213.839 +-- CLK_OUT2___100.000_____30.000______50.0______233.202____213.839 +-- CLK_OUT3____25.000______0.000______50.0______311.133____213.839 +-- +------------------------------------------------------------------------------ +-- "Input Clock Freq (MHz) Input Jitter (UI)" +------------------------------------------------------------------------------ +-- __primary__________50.000____________0.010 + + +-- The following code must appear in the VHDL architecture header: +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component Clock_50to100Split +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Clock out ports + CLK_OUT1 : out std_logic; + CLK_OUT2 : out std_logic; + CLK_OUT3 : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end component; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : Clock_50to100Split + port map + (-- Clock in ports + CLK_IN1 => CLK_IN1, + -- Clock out ports + CLK_OUT1 => CLK_OUT1, + CLK_OUT2 => CLK_OUT2, + CLK_OUT3 => CLK_OUT3, + -- Status and control signals + RESET => RESET, + LOCKED => LOCKED); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ diff --git a/Board/ems11-bb37/Clock_50to100Split.xco b/Board/ems11-bb37/Clock_50to100Split.xco new file mode 100644 index 0000000..397ced1 --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.xco @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Thu Aug 14 16:49:08 2014 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg676 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1 +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2 +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=200.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=100.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=100.000 +CSET clkout2_requested_phase=30.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=true +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=Clock_50to100Split +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=NONE +CSET dcm_clk_out1_port=CLKFX +CSET dcm_clk_out2_port=CLKFX +CSET dcm_clk_out3_port=CLKFX +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=1 +CSET dcm_clkfx_multiply=2 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=20.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=3 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=12 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=20.000 +CSET pll_clkout0_divide=6 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=6 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=30.000 +CSET pll_clkout2_divide=24 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=INTERNAL +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=50.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Single_ended_clock_capable_pin +CSET primary_port=CLK_IN1 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=false +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: 276da5d5 diff --git a/Board/ems11-bb37/Clock_50to100Split.xdc b/Board/ems11-bb37/Clock_50to100Split.xdc new file mode 100644 index 0000000..1339af9 --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.xdc @@ -0,0 +1,67 @@ +# file: Clock_50to100Split.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.2 + +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/Board/ems11-bb37/Clock_50to100Split.xise b/Board/ems11-bb37/Clock_50to100Split.xise new file mode 100644 index 0000000..0c3d4fd --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split.xise @@ -0,0 +1,74 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Board/ems11-bb37/Clock_50to100Split_exdes.ncf b/Board/ems11-bb37/Clock_50to100Split_exdes.ncf new file mode 100644 index 0000000..e4cde90 --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split_exdes.ncf @@ -0,0 +1,73 @@ +# file: Clock_50to100Split_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 100.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz; + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; +PIN "RESET" TIG; + + diff --git a/Board/ems11-bb37/Clock_50to100Split_flist.txt b/Board/ems11-bb37/Clock_50to100Split_flist.txt new file mode 100644 index 0000000..fe2916f --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split_flist.txt @@ -0,0 +1,53 @@ +# Output products list for +Clock_50to100Split.asy +Clock_50to100Split.gise +Clock_50to100Split.sym +Clock_50to100Split.ucf +Clock_50to100Split.vhd +Clock_50to100Split.vho +Clock_50to100Split.xco +Clock_50to100Split.xdc +Clock_50to100Split.xise +Clock_50to100Split\clk_wiz_v3_6_readme.txt +Clock_50to100Split\doc\clk_wiz_v3_6_readme.txt +Clock_50to100Split\doc\clk_wiz_v3_6_vinfo.html +Clock_50to100Split\doc\pg065_clk_wiz.pdf +Clock_50to100Split\example_design\Clock_50to100Split_exdes.ucf +Clock_50to100Split\example_design\Clock_50to100Split_exdes.vhd +Clock_50to100Split\example_design\Clock_50to100Split_exdes.xdc +Clock_50to100Split\implement\implement.bat +Clock_50to100Split\implement\implement.sh +Clock_50to100Split\implement\planAhead_ise.bat +Clock_50to100Split\implement\planAhead_ise.sh +Clock_50to100Split\implement\planAhead_ise.tcl +Clock_50to100Split\implement\planAhead_rdn.bat +Clock_50to100Split\implement\planAhead_rdn.sh +Clock_50to100Split\implement\planAhead_rdn.tcl +Clock_50to100Split\implement\xst.prj +Clock_50to100Split\implement\xst.scr +Clock_50to100Split\simulation\Clock_50to100Split_tb.vhd +Clock_50to100Split\simulation\functional\simcmds.tcl +Clock_50to100Split\simulation\functional\simulate_isim.bat +Clock_50to100Split\simulation\functional\simulate_isim.sh +Clock_50to100Split\simulation\functional\simulate_mti.bat +Clock_50to100Split\simulation\functional\simulate_mti.do +Clock_50to100Split\simulation\functional\simulate_mti.sh +Clock_50to100Split\simulation\functional\simulate_ncsim.sh +Clock_50to100Split\simulation\functional\simulate_vcs.sh +Clock_50to100Split\simulation\functional\wave.do +Clock_50to100Split\simulation\functional\wave.sv +Clock_50to100Split\simulation\timing\Clock_50to100Split_tb.vhd +Clock_50to100Split\simulation\timing\sdf_cmd_file +Clock_50to100Split\simulation\timing\simcmds.tcl +Clock_50to100Split\simulation\timing\simulate_isim.sh +Clock_50to100Split\simulation\timing\simulate_mti.bat +Clock_50to100Split\simulation\timing\simulate_mti.do +Clock_50to100Split\simulation\timing\simulate_mti.sh +Clock_50to100Split\simulation\timing\simulate_ncsim.sh +Clock_50to100Split\simulation\timing\simulate_vcs.sh +Clock_50to100Split\simulation\timing\ucli_commands.key +Clock_50to100Split\simulation\timing\vcs_session.tcl +Clock_50to100Split\simulation\timing\wave.do +Clock_50to100Split_flist.txt +Clock_50to100Split_xmdf.tcl +_xmsgs\pn_parser.xmsgs diff --git a/Board/ems11-bb37/Clock_50to100Split_xmdf.tcl b/Board/ems11-bb37/Clock_50to100Split_xmdf.tcl new file mode 100644 index 0000000..17ef51e --- /dev/null +++ b/Board/ems11-bb37/Clock_50to100Split_xmdf.tcl @@ -0,0 +1,128 @@ +# The package naming convention is _xmdf +package provide Clock_50to100Split_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::Clock_50to100Split_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::Clock_50to100Split_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name Clock_50to100Split +} +# ::Clock_50to100Split_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::Clock_50to100Split_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/simulation/Clock_50to100Split_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path Clock_50to100Split_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module Clock_50to100Split +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/Board/ems11-bb37/EMS11_BB37Toplevel.vhd b/Board/ems11-bb37/EMS11_BB37Toplevel.vhd new file mode 100644 index 0000000..d35a1fd --- /dev/null +++ b/Board/ems11-bb37/EMS11_BB37Toplevel.vhd @@ -0,0 +1,301 @@ +-- Toplevel file for EMS11-BB37 board + +library ieee; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity EMS11_BB37Toplevel is +port +( + -- Housekeeping + CLK50 : in std_logic; + + -- UART + UART1_TXD : out std_logic; + UART1_RXD : in std_logic; + UART1_RTS_N : out std_logic; + UART1_CTS_N : in std_logic; + + -- SDRAM + DR_CAS_N : out std_logic; + DR_CS_N : out std_logic; + DR_RAS_N : out std_logic; + DR_WE_N : out std_logic; + DR_CLK_I : in std_logic; + DR_CLK_O : out std_logic; + DR_CKE : out std_logic; + DR_A : out std_logic_vector(12 downto 0); + DR_D : inout std_logic_vector(15 downto 0); + DR_DQMH : out std_logic; + DR_DQML : out std_logic; + DR_BA : out std_logic_vector(1 downto 0); + + -- SD Card + + FPGA_SD_CDET_N : in std_logic; + FPGA_SD_WPROT_N : in std_logic; + FPGA_SD_CMD : out std_logic; + FPGA_SD_D0 : in std_logic; + FPGA_SD_D1 : in std_logic; -- High Z since we're using SPI-mode + FPGA_SD_D2 : in std_logic; -- High Z since we're using SPI-mode + FPGA_SD_D3 : out std_logic; + FPGA_SD_SCLK : out std_logic; + + -- VGA Connector + UART2_RTS_N : out std_logic; -- Actually used for VGA + -- M1_S : inout std_logic_vector(39 downto 0); + + M1_VGA_RED : out std_logic_vector(7 downto 0); + M1_VGA_GREEN : out std_logic_vector(7 downto 0); + M1_VGA_BLUE : out std_logic_vector(7 downto 0); + M1_VGA_HSYNC : out std_logic; + M1_VGA_VSYNC : out std_logic; + M1_VGA_CLOCK : out std_logic; + M1_VGA_PSAVE_N : out std_logic; + M1_VGA_BLANK_N : out std_logic; + M1_VGA_SYNC_N : out std_logic; + + M1_PS2_A_CLK : inout std_logic; + M1_PS2_A_DATA : inout std_logic; + M1_PS2_B_CLK : inout std_logic; + M1_PS2_B_DATA : inout std_logic; + + -- LEDs + LED1 : out std_logic; + LED2 : out std_logic; + + -- Emus GPIO + GPIO : inout std_logic_vector(15 downto 0); + + -- Buttons + DIAG_N : in std_logic; + RESET_N : in std_logic +); +end entity; + + +architecture rtl of EMS11_BB37Toplevel is + +signal sdram_clk : std_logic; +signal sdram_clk_inv : std_logic; +signal sysclk : std_logic; +signal sysclk_inv : std_logic; +signal clklocked : std_logic; +signal sysclk_slow : std_logic; + +signal vga_red : unsigned(7 downto 0); +signal vga_green : unsigned(7 downto 0); +signal vga_blue : unsigned(7 downto 0); +signal vga_hsync : std_logic; +signal vga_vsync : std_logic; +signal vga_window : std_logic; +signal vga_clock : std_logic; +signal vga_blank : std_logic; +signal vga_sync : std_logic; +signal vga_psave : std_logic; + +-- PS/2 ports +-- alias PS2_MCLK : std_logic is M1_S(35); +-- alias PS2_MDAT : std_logic is M1_S(33); +-- alias PS2_CLK : std_logic is M1_S(37); +-- alias PS2_DAT : std_logic is M1_S(39); + +alias PS2_MCLK : std_logic is M1_PS2_A_CLK; +alias PS2_MDAT : std_logic is M1_PS2_A_DATA; +alias PS2_CLK : std_logic is M1_PS2_B_CLK; +alias PS2_DAT : std_logic is M1_PS2_B_DATA; + +signal ps2m_clk_in : std_logic; +signal ps2m_clk_out : std_logic; +signal ps2m_dat_in : std_logic; +signal ps2m_dat_out : std_logic; + +signal ps2k_clk_in : std_logic; +signal ps2k_clk_out : std_logic; +signal ps2k_dat_in : std_logic; +signal ps2k_dat_out : std_logic; + +begin +UART1_RTS_N<='1'; -- safe default since we're not using handshaking. + +-- DR_CLK_O<='1'; +LED1 <= RESET_N; +LED2 <= DIAG_N; + +ps2m_dat_in<=PS2_MDAT; +PS2_MDAT <= '0' when ps2m_dat_out='0' else 'Z'; +ps2m_clk_in<=PS2_MCLK; +PS2_MCLK <= '0' when ps2m_clk_out='0' else 'Z'; + +ps2k_dat_in<=PS2_DAT; +PS2_DAT <= '0' when ps2k_dat_out='0' else 'Z'; +ps2k_clk_in<=PS2_CLK; +PS2_CLK <= '0' when ps2k_clk_out='0' else 'Z'; + +-- Clock generation. We need a system clock and an SDRAM clock. +-- Limitations of the Spartan 6 mean we need to "forward" the SDRAM clock +-- to the io pin. + +myclock : entity work.Clock_50to100Split +port map( + CLK_IN1 => CLK50, + RESET => '0', + CLK_OUT1 => sysclk, + CLK_OUT2 => sdram_clk, + CLK_OUT3 => sysclk_slow, + LOCKED => clklocked +); + +sysclk_inv <= not sysclk; +sdram_clk_inv <= not sdram_clk; + +ODDR2_inst : ODDR2 +generic map( + DDR_ALIGNMENT => "NONE", + INIT => '0', + SRTYPE => "SYNC") +port map ( + Q => DR_CLK_O, + C0 => sdram_clk, + C1 => sdram_clk_inv, + CE => '1', + D0 => '0', + D1 => '1', + R => '0', -- 1-bit reset input + S => '0' -- 1-bit set input +); + +-- Forward the VGA clock too. + +ODDR2_inst2 : ODDR2 +generic map( + DDR_ALIGNMENT => "NONE", + INIT => '0', + SRTYPE => "SYNC") +port map ( + Q => vga_clock, + C0 => sysclk, + C1 => sysclk_inv, + CE => '1', + D0 => '0', + D1 => '1', + R => '0', -- 1-bit reset input + S => '0' -- 1-bit set input +); + + +-- vga_clock <= sysclk; +vga_sync <= '0'; +vga_blank <= vga_window; +vga_psave <= '1'; + +-- M1_VGA_GREEN(9)<=vga_green(9); +-- M1_VGA_GREEN(8)<=vga_green(8); +M1_VGA_GREEN(7)<=vga_green(7); +M1_VGA_GREEN(6)<=vga_green(6); +M1_VGA_GREEN(5)<=vga_green(5); +M1_VGA_GREEN(4)<=vga_green(4); +M1_VGA_GREEN(3)<=vga_green(3); +M1_VGA_GREEN(2)<=vga_green(2); +M1_VGA_GREEN(1)<=vga_green(1); +M1_VGA_GREEN(0)<=vga_green(0); + +-- M1_VGA_BLUE(9)<=vga_blue(9); +-- M1_VGA_BLUE(8)<=vga_blue(8); +M1_VGA_BLUE(7)<=vga_blue(7); +M1_VGA_BLUE(6)<=vga_blue(6); +M1_VGA_BLUE(5)<=vga_blue(5); +M1_VGA_BLUE(4)<=vga_blue(4); +M1_VGA_BLUE(3)<=vga_blue(3); +M1_VGA_BLUE(2)<=vga_blue(2); +M1_VGA_BLUE(1)<=vga_blue(1); +M1_VGA_BLUE(0)<=vga_blue(0); + +-- M1_VGA_RED(9)<=vga_red(9); +-- M1_VGA_RED(8)<=vga_red(8); +M1_VGA_RED(7)<=vga_red(7); +M1_VGA_RED(6)<=vga_red(6); +M1_VGA_RED(5)<=vga_red(5); +M1_VGA_RED(4)<=vga_red(4); +M1_VGA_RED(3)<=vga_red(3); +M1_VGA_RED(2)<=vga_red(2); +M1_VGA_RED(1)<=vga_red(1); +M1_VGA_RED(0)<=vga_red(0); + +M1_VGA_CLOCK<=vga_clock; +M1_VGA_PSAVE_N<=vga_psave; +M1_VGA_HSYNC<=vga_hsync; +M1_VGA_VSYNC<=vga_vsync; + + +M1_VGA_BLANK_N<=vga_blank; +M1_VGA_SYNC_N<=vga_sync; + +-- M1_S(38)<='1'; + +-- DR_A(12)<='0'; -- Temporary measure + +project: entity work.VirtualToplevel + generic map ( + sdram_rows => 13, + sdram_cols => 10, + sysclk_frequency => 250, -- Sysclk frequency * 10 + fastclk_frequency => 1000 -- Sysclk frequency * 10 + ) + port map ( + clk => sysclk_slow, + clk_fast => sysclk, + reset_in => RESET_N, + + -- VGA + -- vga_red => vga_red(9 downto 2), + -- vga_green => vga_green(9 downto 2), + -- vga_blue => vga_blue(9 downto 2), + + vga_red => vga_red, + vga_green => vga_green, + vga_blue => vga_blue, + vga_hsync => vga_hsync, + vga_vsync => vga_vsync, + vga_window => vga_window, + + -- SDRAM + sdr_data => DR_D, + sdr_addr => DR_A(12 downto 0), + sdr_dqm(1) => DR_DQMH, + sdr_dqm(0) => DR_DQML, + sdr_we => DR_WE_N, + sdr_cas => DR_CAS_N, + sdr_ras => DR_RAS_N, + sdr_cs => DR_CS_N, + sdr_ba => DR_BA, + sdr_cke => DR_CKE, + + -- SD Card + spi_cs => FPGA_SD_D3, + spi_miso => FPGA_SD_D0, + spi_mosi => FPGA_SD_CMD, + spi_clk => FPGA_SD_SCLK, + + -- PS/2 + ps2k_clk_in => ps2k_clk_in, + ps2k_dat_in => ps2k_dat_in, + ps2k_clk_out => ps2k_clk_out, + ps2k_dat_out => ps2k_dat_out, + ps2m_clk_in => ps2m_clk_in, + ps2m_dat_in => ps2m_dat_in, + ps2m_clk_out => ps2m_clk_out, + ps2m_dat_out => ps2m_dat_out, + + -- Emus GPIO + gpio_data => GPIO, + + -- UART + rxd => UART1_RXD, + txd => UART1_TXD +); + +end architecture; diff --git a/Board/ems11-bb37/EMS11_BB37_base.ucf b/Board/ems11-bb37/EMS11_BB37_base.ucf new file mode 100644 index 0000000..a05906e --- /dev/null +++ b/Board/ems11-bb37/EMS11_BB37_base.ucf @@ -0,0 +1,205 @@ +# Generated by makeUCF.ulp developed by Sven Raiser, Tuebingen, Germany +# +# Board: EMS11-FPGA-S6-V1.0.brd +# Part Name: FPGA +# Part pkg: BGA676 +# Created: 04.08.2014 20:00:20 +# Edited: 2014-08-06, by emu + +CONFIG VCCAUX=3.3; + +# +# Clocks & Reset & Switches +# Next lines are just a reminder, how to do it ;-) +# NET "50MHZ" LOC = "xxx"; +# NET "clk" LOC = "xxx"; +# NET "clk" TNM_NET = "clk" | CLOCK_DEDICATED_ROUTE = FALSE; +# TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %; +# +NET "RESET_N" LOC = "B24" | IOSTANDARD = "LVTTL"; +NET "DIAG_N" LOC = "L17" | IOSTANDARD = "LVTTL"; + +NET "CLK50" LOC = "C13" | IOSTANDARD = "LVTTL"; + +# NET "100MHZ_N" LOC = "P22"; +# NET "100MHZ_P" LOC = "P21"; + +NET "LED1" LOC = "L23" | IOSTANDARD = "LVTTL" | DRIVE = 2; # 330R led to gnd +NET "LED2" LOC = "N22" | IOSTANDARD = "LVTTL" | DRIVE = 2; # 330R led to gnd +# NET "FPGA_LED3" LOC = "AF24" | IOSTANDARD = "LVTTL" | DRIVE = 2; # 330R led to gnd + +# NET "CDCE_CLK1" LOC = "N20"; +# NET "CDCE_CLK2" LOC = "M21"; +# NET "CDCE_SCLK" LOC = "K19"; +# NET "CDCE_SDATA" LOC = "K18"; + +# +# UARTs & USB +# +NET "UART1_CTS_N" LOC = "C6"; +NET "UART1_RTS_N" LOC = "C7"; +NET "UART1_RXD" LOC = "D6"; +NET "UART1_TXD" LOC = "A6"; + +# NET "UART2_CTS_N" LOC = "A11"; +# NET "UART2_RTS_N" LOC = "A8"; +# NET "UART2_RXD" LOC = "B8"; +# NET "UART2_TXD" LOC = "A7"; + +# NET "USB_DM" LOC = "F26"; +# NET "USB_DP" LOC = "F24"; + +NET UART* IOSTANDARD = LVTTL | DRIVE = 8 ; +# NET USB* IOSTANDARD = LVTTL | DRIVE = 8 ; +# +# Audio +# +# NET "AUDIO_L" LOC = "C26"; +# NET "AUDIO_R" LOC = "B26"; + +# NET AUDIO* IOSTANDARD = LVTTL | DRIVE = 8 ; + +# +# SDflash 1 & 2 +# +NET "FPGA_SD_CDET_N" LOC = "A2"; +NET "FPGA_SD_CMD" LOC = "C5"; +NET "FPGA_SD_D0" LOC = "A3"; +NET "FPGA_SD_D1" LOC = "A4"; +NET "FPGA_SD_D2" LOC = "A5"; +NET "FPGA_SD_D3" LOC = "B6"; +NET "FPGA_SD_SCLK" LOC = "B4"; + +NET "FPGA_SD_*" IOSTANDARD = LVTTL; + +# NET "MCU_SD_CDET_N" LOC = "D24"; +# NET "MCU_SD_CMD" LOC = "C25"; +# NET "MCU_SD_D0" LOC = "A25"; +# NET "MCU_SD_D1" LOC = "D26"; +# NET "MCU_SD_D2" LOC = "E26"; +# NET "MCU_SD_D3" LOC = "E25"; +# NET "MCU_SD_SCLK" LOC = "B25"; + +# NET "MCU_SD_*" IOSTANDARD = LVTTL; + +# +# EXPMOD1 & EXPMOD2 +# +# NET "EXPMOD1<1>" LOC = "N24"; +# NET "EXPMOD1<2>" LOC = "J26"; +# NET "EXPMOD1<3>" LOC = "N26"; +# NET "EXPMOD1<4>" LOC = "J25"; +# NET "EXPMOD1<5>" LOC = "L26"; +# NET "EXPMOD1<6>" LOC = "L25"; +# NET "EXPMOD1<7>" LOC = "M26"; +# NET "EXPMOD1<8>" LOC = "K26"; +# NET "EXPMOD2<1>" LOC = "M18"; +# NET "EXPMOD2<2>" LOC = "R19"; +# NET "EXPMOD2<3>" LOC = "M19"; +# NET "EXPMOD2<4>" LOC = "T20"; +# NET "EXPMOD2<5>" LOC = "R20"; +# NET "EXPMOD2<6>" LOC = "T22"; +# NET "EXPMOD2<7>" LOC = "U19"; +# NET "EXPMOD2<8>" LOC = "U22"; +# NET EXPMOD_* IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; + + +# +# Ethernet LAN8720 -------------------------------------------------------- +# + +# NET "RMII_#INT/REFCLKO" LOC = "L24"; +# NET "RMII_CRS_DV/MODE2" LOC = "G26"; +# NET "RMII_MDC" LOC = "K24"; +# NET "RMII_MDIO" LOC = "H24"; +# NET "RMII_RXD0/MODE0" LOC = "H26"; +# NET "RMII_RXD1/MODE1" LOC = "G25"; +# NET "RMII_TXD0" LOC = "M24"; +# NET "RMII_TXD1" LOC = "N23"; +# NET "RMII_TXEN" LOC = "M23"; + +# NET "RMII_*" IOSTANDARD = LVTTL; + +# +# VGA, on ADV7511 3x8bit DAC, PS/2 Mouse & keyboard ---------------------------- +# + +NET "M1_VGA_BLANK_N" LOC = "A22"; +NET "M1_VGA_BLUE<0>" LOC = "A19"; +NET "M1_VGA_BLUE<1>" LOC = "C17"; +NET "M1_VGA_BLUE<2>" LOC = "A20"; +NET "M1_VGA_BLUE<3>" LOC = "A17"; +NET "M1_VGA_BLUE<4>" LOC = "A21"; +NET "M1_VGA_BLUE<5>" LOC = "B18"; +NET "M1_VGA_BLUE<6>" LOC = "B22"; +NET "M1_VGA_BLUE<7>" LOC = "D18"; +# NET "M1_VGA_CLOCK_N" LOC = "C20"; +# NET "M1_VGA_CLOCK_P" LOC = "D21"; +NET "M1_VGA_CLOCK" LOC = "D21"; +NET "M1_VGA_GREEN<0>" LOC = "A9"; +NET "M1_VGA_GREEN<1>" LOC = "C9"; +NET "M1_VGA_GREEN<2>" LOC = "C11"; +NET "M1_VGA_GREEN<3>" LOC = "B12"; +NET "M1_VGA_GREEN<4>" LOC = "B14"; +NET "M1_VGA_GREEN<5>" LOC = "D14"; +NET "M1_VGA_GREEN<6>" LOC = "B16"; +NET "M1_VGA_GREEN<7>" LOC = "C15"; +NET "M1_VGA_HSYNC" LOC = "C21"; +NET "M1_PS2_A_CLK" LOC = "B23"; +NET "M1_PS2_A_DATA" LOC = "A23"; +NET "M1_PS2_B_CLK" LOC = "L19"; +NET "M1_PS2_B_DATA" LOC = "L18"; +NET "M1_VGA_RED<0>" LOC = "A12"; +NET "M1_VGA_RED<1>" LOC = "A13"; +NET "M1_VGA_RED<2>" LOC = "A14"; +NET "M1_VGA_RED<3>" LOC = "C14"; +NET "M1_VGA_RED<4>" LOC = "A15"; +NET "M1_VGA_RED<5>" LOC = "A16"; +NET "M1_VGA_RED<6>" LOC = "A18"; +NET "M1_VGA_RED<7>" LOC = "C19"; +NET "M1_VGA_SYNC_N" LOC = "C18"; +NET "M1_VGA_VSYNC" LOC = "B20"; + +NET M1_* IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST; + +# +# Not used on QTE-Right --------------------------------------------------- +# + +# NET "FU_23" LOC = "Y21"; +# NET "FU_24" LOC = "Y20"; +# NET "FU_25" LOC = "V19"; +# NET "FU_26" LOC = "V20"; +# NET "FU_27" LOC = "U21"; +# +# SDR SDRAM if used, is in ems11-bb37-sdram.ucf ------------------------------------------ +# + +# +# DDR3 SDRAM if used, is in ems11-bb37-ddr3.ucf ---------------------------------- +# + +# +# VG96 connector, please use the corresponding ems11-bb37-vg96.ucf file for the used module +# + + +# +# The usual remaining pins ;-) -------------------------------------------- +# + +# NET "FPGA_CCLK_INTERNAL" LOC = "AD22"; +# NET "FPGA_CSO" LOC = "AF4"; +# NET "FPGA_DONE" LOC = "AF23"; +# NET "FPGA_INIT" LOC = "AE4"; + +# NET "FPGA_M0" LOC = "AF22"; +# NET "FPGA_M1" LOC = "AD16"; +# NET "FPGA_MISO_INTERNAL" LOC = "AD20"; +# NET "FPGA_MOSI" LOC = "AF20"; +# NET "FPGA_PROG" LOC = "AF3"; + +# NET "FPGA_TCK" LOC = "E21"; +# NET "FPGA_TDI" LOC = "F20"; +# NET "FPGA_TDO" LOC = "A24"; +# NET "FPGA_TMS" LOC = "C23"; \ No newline at end of file diff --git a/Board/ems11-bb37/EMS11_BB37_ddr3.ucf b/Board/ems11-bb37/EMS11_BB37_ddr3.ucf new file mode 100644 index 0000000..345a0ab --- /dev/null +++ b/Board/ems11-bb37/EMS11_BB37_ddr3.ucf @@ -0,0 +1,64 @@ +# Generated by makeUCF.ulp developed by Sven Raiser, Tuebingen, Germany +# +# Board: EMS11-FPGA-S6-V1.0.brd +# Part Name: FPGA +# Part pkg: BGA676 +# Created: 04.08.2014 20:00:20 +# Edited: 2014-08-06, by emu + +CONFIG VCCAUX=3.3; + +# +# DDR3 SDRAM MT41J256M16HA-107:E +# +# NET "DDR_A<0>" LOC = "N7"; +# NET "DDR_A<1>" LOC = "N6"; +# NET "DDR_A<2>" LOC = "R9"; +# NET "DDR_A<3>" LOC = "P7"; +# NET "DDR_A<4>" LOC = "N9"; +# NET "DDR_A<5>" LOC = "R2"; +# NET "DDR_A<6>" LOC = "R1"; +# NET "DDR_A<7>" LOC = "P10"; +# NET "DDR_A<8>" LOC = "N4"; +# NET "DDR_A<9>" LOC = "N3"; +# NET "DDR_A<10>" LOC = "M10"; +# NET "DDR_A<11>" LOC = "L3"; +# NET "DDR_A<12>" LOC = "M8"; +# NET "DDR_A<13>" LOC = "M6"; +# NET "DDR_A<14>" LOC = "M4"; +# NET "DDR_BA<0>" LOC = "P3"; +# NET "DDR_BA<1>" LOC = "P1"; +# NET "DDR_BA<2>" LOC = "N5"; +# NET "DDR_CAS_N" LOC = "P8"; +# NET "DDR_CKE" LOC = "M9"; +# NET "DDR_CK_N" LOC = "R3"; +# NET "DDR_CK_P" LOC = "R4"; +# NET "DDR_DQ<0>" LOC = "Y3"; +# NET "DDR_DQ<1>" LOC = "Y1"; +# NET "DDR_DQ<2>" LOC = "W2"; +# NET "DDR_DQ<3>" LOC = "W1"; +# NET "DDR_DQ<4>" LOC = "T3"; +# NET "DDR_DQ<5>" LOC = "T1"; +# NET "DDR_DQ<6>" LOC = "U2"; +# NET "DDR_DQ<7>" LOC = "U1"; +# NET "DDR_DQ<8>" LOC = "AA2"; +# NET "DDR_DQ<9>" LOC = "AA1"; +# NET "DDR_DQ<10>" LOC = "AE2"; +# NET "DDR_DQ<11>" LOC = "AE1"; +# NET "DDR_DQ<12>" LOC = "AD3"; +# NET "DDR_DQ<13>" LOC = "AD1"; +# NET "DDR_DQ<14>" LOC = "AB3"; +# NET "DDR_DQ<15>" LOC = "AB1"; +# NET "DDR_LDM" LOC = "W3"; +# NET "DDR_LDQS_N" LOC = "V1"; +# NET "DDR_LDQS_P" LOC = "V3"; +# NET "DDR_ODT" LOC = "P6"; +# NET "DDR_RAS_N" LOC = "N8"; +# NET "DDR_RESET_N" LOC = "L4"; +# NET "DDR_RZQ" LOC = "AC7"; +# NET "DDR_UDM" LOC = "V4"; +# NET "DDR_UDQS_N" LOC = "AC1"; +# NET "DDR_UDQS_P" LOC = "AC2"; +# NET "DDR_WE_N" LOC = "P5"; +# NET "DDR_ZIO" LOC = "AE3"; + diff --git a/Board/ems11-bb37/EMS11_BB37_sdram.ucf b/Board/ems11-bb37/EMS11_BB37_sdram.ucf new file mode 100644 index 0000000..18d872d --- /dev/null +++ b/Board/ems11-bb37/EMS11_BB37_sdram.ucf @@ -0,0 +1,58 @@ +# Generated by makeUCF.ulp developed by Sven Raiser, Tuebingen, Germany +# +# Board: EMS11-FPGA-S6-V1.0.brd +# Part Name: FPGA +# Part pkg: BGA676 +# Created: 04.08.2014 20:00:20 +# Edited: 2014-08-06, by emu + +CONFIG VCCAUX=3.3; + +# +# SDR SDRAM MT48LC32M16ARP-75C +# +NET "DR_A<0>" LOC = "W24"; +NET "DR_A<1>" LOC = "V23"; +NET "DR_A<2>" LOC = "U23"; +NET "DR_A<3>" LOC = "T24"; +NET "DR_A<4>" LOC = "N25"; +NET "DR_A<5>" LOC = "P26"; +NET "DR_A<6>" LOC = "P24"; +NET "DR_A<7>" LOC = "R26"; +NET "DR_A<8>" LOC = "R25"; +NET "DR_A<9>" LOC = "T26"; +NET "DR_A<10>" LOC = "Y22"; +NET "DR_A<11>" LOC = "U24"; +NET "DR_A<12>" LOC = "R23"; +NET "DR_BA<0>" LOC = "AA23"; +NET "DR_BA<1>" LOC = "Y24"; +NET "DR_CAS_N" LOC = "AC24"; +NET "DR_CKE" LOC = "R24"; +NET "DR_CLK_O" LOC = "U26"; +NET "DR_CLK_I" LOC = "U25"; +NET "DR_CS_N" LOC = "AA24"; +NET "DR_D<0>" LOC = "AE25"; +NET "DR_D<1>" LOC = "AD24"; +NET "DR_D<2>" LOC = "AC26"; +NET "DR_D<3>" LOC = "AB26"; +NET "DR_D<4>" LOC = "AA26"; +NET "DR_D<5>" LOC = "Y26"; +NET "DR_D<6>" LOC = "W26"; +NET "DR_D<7>" LOC = "V26"; +NET "DR_D<8>" LOC = "V24"; +NET "DR_D<9>" LOC = "W25"; +NET "DR_D<10>" LOC = "AA25"; +NET "DR_D<11>" LOC = "AB24"; +NET "DR_D<12>" LOC = "AC25"; +NET "DR_D<13>" LOC = "AD26"; +NET "DR_D<14>" LOC = "AE26"; +NET "DR_D<15>" LOC = "AF25"; +NET "DR_DQMH" LOC = "T23"; +NET "DR_DQML" LOC = "AE24"; +NET "DR_RAS_N" LOC = "AA22"; +NET "DR_WE_N" LOC = "AC23"; + + +NET DR_* IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST; +NET DR_CLK_O BUFG = CLK; +NET DR_D<*> NODELAY; \ No newline at end of file diff --git a/Board/ems11-bb37/EMS11_MIO_TEST_V0.0.ucf b/Board/ems11-bb37/EMS11_MIO_TEST_V0.0.ucf new file mode 100644 index 0000000..4f9aaf0 --- /dev/null +++ b/Board/ems11-bb37/EMS11_MIO_TEST_V0.0.ucf @@ -0,0 +1,39 @@ +# Generated by makeUCF.ulp developed by Sven Raiser, Tuebingen, Germany +# + +# Board: ems11-mio-test-v0.0 +# usable on ems11-bb-v2.1 and ems11-bb-v3.0 +# Part Name: FPGA +# Part pkg: BGA676 +# Created: 24.01.2014 15:09:19 +# Edited: 2014-06-10 + +NET "GPIO<0>" LOC = "T1"; #-- IO 0 +NET "GPIO<1>" LOC = "R1"; #-- IO 1 +NET "GPIO<2>" LOC = "N1"; #-- IO 2 +NET "GPIO<3>" LOC = "N2"; #-- IO 3 +NET "GPIO<4>" LOC = "K1"; #-- IO 4 +NET "GPIO<5>" LOC = "L2"; #-- IO 5 +NET "GPIO<6>" LOC = "L1"; #-- IO 6 +NET "GPIO<7>" LOC = "G1"; #-- IO 7 +NET "GPIO<8>" LOC = "J2"; #-- IO 8 +NET "GPIO<9>" LOC = "J1"; #-- IO 9 + +NET "GPIO<10>" LOC = "E3"; #-- TO LOCK THEM TO THE VG96, NO connection to MIO +NET "GPIO<11>" LOC = "D3"; #-- TO LOCK THEM TO THE VG96, NO connection to MIO +NET "GPIO<12>" LOC = "C4"; #-- TO LOCK THEM TO THE VG96, NO connection to MIO +NET "GPIO<13>" LOC = "C3"; #-- TO LOCK THEM TO THE VG96, NO connection to MIO + + +NET "GPIO<14>" LOC = "U2"; #-- RESET +NET "GPIO<15>" LOC = "W1"; #-- CLK + +# NET "VC_A6_I2C_SDA" LOC = "AA1"; +# NET "VC_A7_I2C_SCL" LOC = "W2"; +# NET "VC_A9_IA<1>" LOC = "V1"; +# NET "VC_A11_IA<2>" LOC = "U1"; +# NET "VC_A13_IA<3>" LOC = "R2"; +# NET "VC_A21_IA<4>" LOC = "M1"; + +NET "GPIO*" IOSTANDARD = LVTTL | DRIVE = 4; + diff --git a/Board/ems11-bb37/coregen.cgp b/Board/ems11-bb37/coregen.cgp new file mode 100644 index 0000000..e15b0f7 --- /dev/null +++ b/Board/ems11-bb37/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = fgg676 +SET speedgrade = -3 +SET verilogsim = false +SET vhdlsim = true diff --git a/Board/ems11-bb37/edit_Clock_50to100Split.tcl b/Board/ems11-bb37/edit_Clock_50to100Split.tcl new file mode 100644 index 0000000..2a1a9a8 --- /dev/null +++ b/Board/ems11-bb37/edit_Clock_50to100Split.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "Clock_50to100Split" xc6slx45-3fgg676 VHDL ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result diff --git a/Board/mist/Clock_27to100Split.cmp b/Board/mist/Clock_27to100Split.cmp new file mode 100644 index 0000000..ee5e254 --- /dev/null +++ b/Board/mist/Clock_27to100Split.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component Clock_27to100Split + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/Board/mist/Clock_27to100Split.ppf b/Board/mist/Clock_27to100Split.ppf new file mode 100644 index 0000000..d1c78cb --- /dev/null +++ b/Board/mist/Clock_27to100Split.ppf @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/Board/mist/Clock_27to100Split.qip b/Board/mist/Clock_27to100Split.qip new file mode 100644 index 0000000..d9d8af6 --- /dev/null +++ b/Board/mist/Clock_27to100Split.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_27to100Split.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_27to100Split.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_27to100Split.ppf"] diff --git a/Board/mist/Clock_27to100Split.vhd b/Board/mist/Clock_27to100Split.vhd new file mode 100644 index 0000000..7e71cae --- /dev/null +++ b/Board/mist/Clock_27to100Split.vhd @@ -0,0 +1,435 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: Clock_27to100Split.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY Clock_27to100Split IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END Clock_27to100Split; + + +ARCHITECTURE SYN OF clock_27to100split IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 27, + clk0_duty_cycle => 50, + clk0_multiply_by => 100, + clk0_phase_shift => "0", + clk1_divide_by => 27, + clk1_duty_cycle => 50, + clk1_multiply_by => 100, + clk1_phase_shift => "-1000", + clk2_divide_by => 27, + clk2_duty_cycle => 50, + clk2_multiply_by => 25, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=Clock_27to100Split", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-1.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_50to100Split.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "100" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "100" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1000" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100Split.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100Split.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100Split.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100Split.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100Split.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100Split_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_27to100Split.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_27to100Split.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_27to100Split.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_27to100Split.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_27to100Split.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_27to100Split_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Board/mist/MIST_Toplevel.vhd b/Board/mist/MIST_Toplevel.vhd new file mode 100644 index 0000000..497bd5f --- /dev/null +++ b/Board/mist/MIST_Toplevel.vhd @@ -0,0 +1,493 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity MIST_Toplevel is + port + ( + CLOCK_27 : in std_logic_vector(1 downto 0); + + LED : out std_logic; + + UART_TX : out STD_LOGIC; + UART_RX : in STD_LOGIC; + + SDRAM_DQ : inout std_logic_vector(15 downto 0); + SDRAM_A : out std_logic_vector(12 downto 0); + SDRAM_DQMH : out STD_LOGIC; + SDRAM_DQML : out STD_LOGIC; + SDRAM_nWE : out STD_LOGIC; + SDRAM_nCAS : out STD_LOGIC; + SDRAM_nRAS : out STD_LOGIC; + SDRAM_nCS : out STD_LOGIC; + SDRAM_BA : out std_logic_vector(1 downto 0); + SDRAM_CLK : out STD_LOGIC; + SDRAM_CKE : out STD_LOGIC; + + SPI_DO : inout std_logic; + SPI_DI : in std_logic; + SPI_SCK : in STD_LOGIC; + SPI_SS2 : in STD_LOGIC; -- FPGA + SPI_SS3 : in STD_LOGIC; -- OSD + SPI_SS4 : in STD_LOGIC; -- "sniff" mode + CONF_DATA0 : in std_logic; -- SPI_SS for user_io + + VGA_HS : buffer STD_LOGIC; + VGA_VS : buffer STD_LOGIC; + VGA_R : out unsigned(5 downto 0); + VGA_G : out unsigned(5 downto 0); + VGA_B : out unsigned(5 downto 0); + + AUDIO_L : out std_logic; + AUDIO_R : out std_logic + ); +END entity; + +architecture rtl of MIST_Toplevel is + +signal reset : std_logic; +signal pll_locked : std_logic; +signal clk_fast : std_logic; +signal clk : std_logic; + +signal audiol : std_logic_vector(15 downto 0); +signal audior : std_logic_vector(15 downto 0); + +signal vga_tred : unsigned(7 downto 0); +signal vga_tgreen : unsigned(7 downto 0); +signal vga_tblue : unsigned(7 downto 0); +signal vga_window : std_logic; + +-- core video to be fed into osd +signal core_r : std_logic_vector(5 downto 0); +signal core_g : std_logic_vector(5 downto 0); +signal core_b : std_logic_vector(5 downto 0); +signal core_vs: std_logic; +signal core_hs: std_logic; +signal osdclk: std_logic; + +-- user_io +signal buttons: std_logic_vector(1 downto 0); +signal status: std_logic_vector(7 downto 0); +signal joy_0: std_logic_vector(5 downto 0); +signal joy_1: std_logic_vector(5 downto 0); +signal joyn_0: std_logic_vector(5 downto 0); +signal joyn_1: std_logic_vector(5 downto 0); +signal joy_ana_0: std_logic_vector(15 downto 0); +signal joy_ana_1: std_logic_vector(15 downto 0); +signal txd: std_logic; +signal par_out_data: std_logic_vector(7 downto 0); +signal par_out_strobe: std_logic; + +-- signals to connect sd card emulation with io controller +signal sd_lba: std_logic_vector(31 downto 0); +signal sd_rd: std_logic; +signal sd_wr: std_logic; +signal sd_ack: std_logic; +signal sd_conf: std_logic; +signal sd_sdhc: std_logic; +signal sd_allow_sdhc: std_logic; +signal sd_allow_sdhcD: std_logic; +signal sd_allow_sdhcD2: std_logic; +signal sd_allow_sdhc_changed: std_logic; +-- data from io controller to sd card emulation +signal sd_data_in: std_logic_vector(7 downto 0); +signal sd_data_in_strobe: std_logic; +signal sd_data_out: std_logic_vector(7 downto 0); +signal sd_data_out_strobe: std_logic; + +-- sd card emulation +signal sd_cs: std_logic; +signal sd_sck: std_logic; +signal sd_sdi: std_logic; +signal sd_sdo: std_logic; + +-- PS/2 +signal ps2_clk : std_logic; +signal ps2counter : unsigned(10 downto 0); + +-- PS/2 Keyboard +signal ps2_keyboard_clk_in : std_logic; +signal ps2_keyboard_dat_in : std_logic; +signal ps2_keyboard_clk_mix : std_logic; +signal ps2_keyboard_clk_out : std_logic; +signal ps2_keyboard_dat_out : std_logic; + +-- PS/2 Mouse +signal ps2_mouse_clk_in : std_logic; +signal ps2_mouse_dat_in : std_logic; +signal ps2_mouse_clk_mix : std_logic; +signal ps2_mouse_clk_out : std_logic; +signal ps2_mouse_dat_out : std_logic; + +-- Sigma Delta audio +COMPONENT hybrid_pwm_sd + PORT + ( + clk : IN STD_LOGIC; + n_reset : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dout : OUT STD_LOGIC + ); +END COMPONENT; + +COMPONENT video_vga_dither + GENERIC ( outbits : INTEGER := 4 ); + PORT + ( + clk : IN STD_LOGIC; + hsync : IN STD_LOGIC; + vsync : IN STD_LOGIC; + vid_ena : IN STD_LOGIC; + iRed : IN UNSIGNED(7 DOWNTO 0); + iGreen : IN UNSIGNED(7 DOWNTO 0); + iBlue : IN UNSIGNED(7 DOWNTO 0); + oRed : OUT UNSIGNED(outbits-1 DOWNTO 0); + oGreen : OUT UNSIGNED(outbits-1 DOWNTO 0); + oBlue : OUT UNSIGNED(outbits-1 DOWNTO 0) + ); +END COMPONENT; + +component osd +generic ( OSD_COLOR : integer ); +port ( pclk, sck, ss, sdi, hs_in, vs_in : in std_logic; + red_in, blue_in, green_in : in std_logic_vector(5 downto 0); + red_out, blue_out, green_out : out std_logic_vector(5 downto 0); + hs_out, vs_out : out std_logic + ); +end component osd; + +-- the config string is read by the io controller and allows simple core specific +-- controls +constant CONF_STR : string := "TG68MiniSOC;;T1,Reset"; + +function to_slv(s: string) return std_logic_vector is + constant ss: string(1 to s'length) := s; + variable rval: std_logic_vector(1 to 8 * s'length); + variable p: integer; + variable c: integer; + + begin + for i in ss'range loop + p := 8 * i; + c := character'pos(ss(i)); + rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); + end loop; + return rval; + +end function; + + +component user_io + generic ( STRLEN : integer := 0 ); + port ( + SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic; + SPI_MISO : out std_logic; + conf_str : in std_logic_vector(8*STRLEN-1 downto 0); + joystick_0 : out std_logic_vector(5 downto 0); + joystick_1 : out std_logic_vector(5 downto 0); + joystick_analog_0 : out std_logic_vector(15 downto 0); + joystick_analog_1 : out std_logic_vector(15 downto 0); + status: out std_logic_vector(7 downto 0); + switches : out std_logic_vector(1 downto 0); + buttons : out std_logic_vector(1 downto 0); + sd_lba : in std_logic_vector(31 downto 0); + sd_rd : in std_logic; + sd_wr : in std_logic; + sd_ack : out std_logic; + sd_conf : in std_logic; + sd_sdhc : in std_logic; + sd_dout : out std_logic_vector(7 downto 0); + sd_dout_strobe : out std_logic; + sd_din : in std_logic_vector(7 downto 0); + sd_din_strobe : out std_logic; + ps2_clk : in std_logic; + ps2_kbd_clk : out std_logic; + ps2_kbd_data : out std_logic; + ps2_mouse_clk : out std_logic; + ps2_mouse_data : out std_logic; + serial_data : in std_logic_vector(7 downto 0); + serial_strobe : in std_logic + ); + end component user_io; + +component mist_console + generic ( CLKFREQ : integer := 100 ); + port ( clk : in std_logic; + n_reset: in std_logic; + ser_in : in std_logic; + par_out_data : out std_logic_vector(7 downto 0); + par_out_strobe : out std_logic + ); + end component mist_console; + +component sd_card + port ( io_lba : out std_logic_vector(31 downto 0); + io_rd : out std_logic; + io_wr : out std_logic; + io_ack : in std_logic; + io_sdhc : out std_logic; + io_conf : out std_logic; + io_din : in std_logic_vector(7 downto 0); + io_din_strobe : in std_logic; + io_dout : out std_logic_vector(7 downto 0); + io_dout_strobe : in std_logic; + + allow_sdhc : in std_logic; + + sd_cs : in std_logic; + sd_sck : in std_logic; + sd_sdi : in std_logic; + sd_sdo : out std_logic + ); + end component sd_card; + +begin + + + mypll : entity work.Clock_27to100Split + port map ( + inclk0 => CLOCK_27(0), + c0 => clk_fast, + c1 => SDRAM_CLK, + c2 => clk, + locked => pll_locked + ); + + +-- reset from IO controller +-- status bit 0 is always triggered by the i ocontroller on its own reset +-- status bit 1 is driven by the "T2,Reset" entry in the config string +-- button 1 is the core specfic button in the mists front +reset <= '0' when status(0)='1' or status(1)='1' or buttons(1)='1' else '1'; + +process(clk) +begin +-- ps2_keyboard_clk_mix <= ps2_keyboard_clk_in and (ps2_clk or ps2_keyboard_dat_out); + ps2_keyboard_clk_mix <= ps2_keyboard_clk_in; -- and (ps2_clk or ps2_keyboard_dat_out); + ps2_mouse_clk_mix <= ps2_mouse_clk_in; -- and (ps2_clk or ps2_mouse_dat_out); + if rising_edge(clk) then + ps2counter<=ps2counter+1; + if ps2counter=1200 then + ps2_clk<=not ps2_clk; + ps2counter<=(others => '0'); + end if; + end if; +end process; + + +mist_console_d: component mist_console + generic map + ( CLKFREQ => 100) + port map + ( + clk => clk_fast, + n_reset => reset, + ser_in => txd, + par_out_data => par_out_data, + par_out_strobe => par_out_strobe + ); + + +sd_card_d: component sd_card + port map + ( + -- connection to io controller + io_lba => sd_lba, + io_rd => sd_rd, + io_wr => sd_wr, + io_ack => sd_ack, + io_conf => sd_conf, + io_sdhc => sd_sdhc, + io_din => sd_data_in, + io_din_strobe => sd_data_in_strobe, + io_dout => sd_data_out, + io_dout_strobe => sd_data_out_strobe, + + allow_sdhc => '1', + + -- connection to host + sd_cs => sd_cs, + sd_sck => sd_sck, + sd_sdi => sd_sdi, + sd_sdo => sd_sdo + ); + +-- prevent joystick signals from being optimzed away +LED <= '0' when ((joy_ana_0 /= joy_ana_1) AND (joy_0 /= joy_1)) else '1'; + +user_io_d : user_io + generic map (STRLEN => CONF_STR'length) + port map ( + SPI_CLK => SPI_SCK, + SPI_SS_IO => CONF_DATA0, + SPI_MISO => SPI_DO, + SPI_MOSI => SPI_DI, + conf_str => to_slv(CONF_STR), + status => status, + + -- connection to io controller + sd_lba => sd_lba, + sd_rd => sd_rd, + sd_wr => sd_wr, + sd_ack => sd_ack, + sd_sdhc => sd_sdhc, + sd_conf => sd_conf, + sd_dout => sd_data_in, + sd_dout_strobe => sd_data_in_strobe, + sd_din => sd_data_out, + sd_din_strobe => sd_data_out_strobe, + + joystick_0 => joy_0, + joystick_1 => joy_1, + joystick_analog_0 => joy_ana_0, + joystick_analog_1 => joy_ana_1, +-- switches => switches, + BUTTONS => buttons, + ps2_clk => ps2_clk, + ps2_kbd_clk => ps2_keyboard_clk_in, + ps2_kbd_data => ps2_keyboard_dat_in, + ps2_mouse_clk => ps2_mouse_clk_in, + ps2_mouse_data => ps2_mouse_dat_in, + serial_data => par_out_data, + serial_strobe => par_out_strobe + ); + + joyn_0 <= not joy_0; + joyn_1 <= not joy_1; + + +mydither : component video_vga_dither + generic map ( + outbits => 6 + ) + port map ( + clk => clk_fast, + hsync => core_hs, + vsync => core_vs, + vid_ena => vga_window, + iRed => vga_tred, + iGreen => vga_tgreen, + iBlue => vga_tblue, + std_logic_vector(oRed) => core_r, + std_logic_vector(oGreen) => core_g, + std_logic_vector(oBlue) => core_b + ); + + +-- OSD pixel clock from system clock +process(clk_fast) +variable clk_div : unsigned(7 downto 0); +begin + if rising_edge(clk_fast) then + clk_div := clk_div + 1; + end if; + + osdclk <= clk_div(1); +end process; + +osd_inst : component osd + generic map (OSD_COLOR => 6) + port map ( + pclk => osdclk, + sdi => SPI_DI, + sck => SPI_SCK, + ss => SPI_SS3, + red_in => core_r, + green_in => core_g, + blue_in => core_b, + hs_in => core_hs, + vs_in => core_vs, + unsigned(red_out) => VGA_R, + unsigned(green_out) => VGA_G, + unsigned(blue_out) => VGA_B, + hs_out => VGA_HS, + vs_out => VGA_VS + ); + + +-- Do we have audio? If so, instantiate a two DAC channels. +leftsd: component hybrid_pwm_sd + port map + ( + clk => clk_fast, + n_reset => reset, + din(15) => not audiol(15), + din(14 downto 0) => std_logic_vector(audiol(14 downto 0)), + dout => AUDIO_L + ); + +rightsd: component hybrid_pwm_sd + port map + ( + clk => clk_fast, + n_reset => reset, + din(15) => not audior(15), + din(14 downto 0) => std_logic_vector(audior(14 downto 0)), + dout => AUDIO_R + ); + + +mytg68test : entity work.VirtualToplevel + generic map( + sdram_rows => 13, + sdram_cols => 9, + sysclk_frequency => 250, + fastclk_frequency => 1000 + ) + port map( + clk => clk, + clk_fast => clk_fast, + reset_in => reset, + + -- SDRAM + sdr_addr => SDRAM_A, + sdr_data => SDRAM_DQ, + sdr_ba => SDRAM_BA, + sdr_cke => SDRAM_CKE, + sdr_dqm(1) => SDRAM_DQMH, + sdr_dqm(0) => SDRAM_DQML, + sdr_cs => SDRAM_nCS, + sdr_we => SDRAM_nWE, + sdr_cas => SDRAM_nCAS, + sdr_ras => SDRAM_nRAS, + + -- VGA + unsigned(vga_red) => vga_tred, + unsigned(vga_green) => vga_tgreen, + unsigned(vga_blue) => vga_tblue, + + vga_hsync => core_hs, + vga_vsync => core_vs, + + vga_window => vga_window, + + -- UART + rxd => UART_RX, + txd => txd, + + -- PS/2 + ps2k_clk_in => ps2_keyboard_clk_in, + ps2k_dat_in => ps2_keyboard_dat_in, + ps2k_clk_out => ps2_keyboard_clk_out, + ps2k_dat_out => ps2_keyboard_dat_out, + ps2m_clk_in => ps2_mouse_clk_in, + ps2m_dat_in => ps2_mouse_dat_in, + ps2m_clk_out => ps2_mouse_clk_out, + ps2m_dat_out => ps2_mouse_dat_out, + + -- SD Card interface + spi_cs => sd_cs, + spi_miso => sd_sdo, + spi_mosi => sd_sdi, + spi_clk => sd_sck, + + -- Audio - FIXME abstract this out, too. + std_logic_vector(audio_l) => audiol, + std_logic_vector(audio_r) => audior + + -- LEDs + ); + + +end architecture; diff --git a/Board/mist/mist.sdc b/Board/mist/mist.sdc new file mode 100644 index 0000000..3977b56 --- /dev/null +++ b/Board/mist/mist.sdc @@ -0,0 +1,129 @@ +## Generated SDC file "hello_led.out.sdc" + +## Copyright (C) 1991-2011 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition" + +## DATE "Fri Jul 06 23:05:47 2012" + +## +## DEVICE "EP3C25Q240C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk_27} -period 37.037 -waveform { 0.000 0.500 } [get_ports {CLOCK_27[0]}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + +derive_pll_clocks +create_generated_clock -name sd1clk_pin -source [get_pins {mypll|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {SDRAM_CLK}] +create_generated_clock -name sysclk -source [get_pins {mypll|altpll_component|auto_generated|pll1|clk[1]}] + +#************************************************************** +# Set Clock Latency +#************************************************************** + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +derive_clock_uncertainty; + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -clock sd1clk_pin -max 5.8 [get_ports SDRAM_DQ*] +set_input_delay -clock sd1clk_pin -min 3.2 [get_ports SDRAM_DQ*] + +# Delays for async signals - not necessary, but might as well avoid +# having unconstrained ports in the design +set_input_delay -clock sysclk -min 0.0 [get_ports {UART_RX}] +set_input_delay -clock sysclk -max 0.0 [get_ports {UART_RX}] + + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -clock sd1clk_pin -max 1.5 [get_ports SDRAM_*] +set_output_delay -clock sd1clk_pin -min -0.8 [get_ports SDRAM_*] +set_output_delay -clock sd1clk_pin -max 0.5 [get_ports SDRAM_CLK] +set_output_delay -clock sd1clk_pin -min 0.5 [get_ports SDRAM_CLK] + +# Delays for async signals - not necessary, but might as well avoid +# having unconstrained ports in the design +#set_output_delay -clock sysclk -min 0.0 [get_ports UART_TX] +#set_output_delay -clock sysclk -max 0.0 [get_ports UART_TX] + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +# Asynchronous signal, so not important timing-wise +set_false_path -from {*uart|txd} -to {UART_TX} + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +#set_multicycle_path -from [get_clocks {mypll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {sd2clk_pin}] -setup -end 2 +#set_multicycle_path -from [get_clocks {mypll2|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {sd2clk_pin}] -setup -end 2 + +set_multicycle_path -from [get_clocks {sd1clk_pin}] -to [get_clocks {mypll|altpll_component|auto_generated|pll1|clk[1]}] -setup -end 2 + +set_multicycle_path -through [get_nets {*zpu|Mult0*}] -setup -end 2 +set_multicycle_path -through [get_nets {*zpu|Mult0*}] -hold -end 2 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** diff --git a/Board/mist/mist_console.v b/Board/mist/mist_console.v new file mode 100644 index 0000000..a242a17 --- /dev/null +++ b/Board/mist/mist_console.v @@ -0,0 +1,59 @@ +// mist_console.v +// +// receive serial data and forware it to the io controller +// + +module mist_console #(parameter CLKFREQ=100) ( + // system interface + input clk, // 125MHz + input n_reset, + + input ser_in, + + // input par_out_ + output [7:0] par_out_data, + output par_out_strobe +); + +localparam TICKSPERBIT = (CLKFREQ*1000000)/115200; + +assign par_out_data = rx_byte; +assign par_out_strobe = strobe; + +reg strobe; +reg [7:0] rx_byte /* synthese noprune */; +reg [5:0] state; +reg [15:0] recheck; + +always @(posedge clk) begin + if(!n_reset) begin + state <= 6'd0; // idle + strobe <= 1'b0; + end else begin + if(state == 0) begin + + // detecting low in idle state + if(!ser_in) begin + recheck <= 3*TICKSPERBIT/2; + state <= 9; + strobe <= 1'b0; + end + end else begin + if(recheck != 0) + recheck <= recheck - 1; + else begin + if(state > 1) + rx_byte <= { ser_in, rx_byte[7:1]}; + + recheck <= TICKSPERBIT; + state <= state - 1; + + // last bit is stop bit and needs to be '1' + if((state == 1) && (ser_in == 1)) + strobe <= 1'b1; + end + end + end +end + +endmodule diff --git a/Board/mist/osd.v b/Board/mist/osd.v new file mode 100644 index 0000000..a654b40 --- /dev/null +++ b/Board/mist/osd.v @@ -0,0 +1,182 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input pclk, + + // SPI interface + input sck, + input ss, + input sdi, + + // VGA signals coming from core + input [5:0] red_in, + input [5:0] green_in, + input [5:0] blue_in, + input hs_in, + input vs_in, + + // VGA signals going to video connector + output [5:0] red_out, + output [5:0] green_out, + output [5:0] blue_out, + output hs_out, + output vs_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg [7:0] sbuf; +reg [7:0] cmd; +reg [4:0] cnt; +reg [10:0] bcnt; +reg osd_enable; + +reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge sck, posedge ss) begin + if(ss == 1'b1) begin + cnt <= 5'd0; + bcnt <= 11'd0; + end else begin + sbuf <= { sbuf[6:0], sdi}; + + // 0:7 is command, rest payload + if(cnt < 15) + cnt <= cnt + 4'd1; + else + cnt <= 4'd8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], sdi}; + + // lower three command bits are line address + bcnt <= { sbuf[1:0], sdi, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) + osd_enable <= sdi; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], sdi}; + bcnt <= bcnt + 11'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg hsD, hsD2; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high; +wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] }; + +always @(posedge pclk) begin + // bring hsync into local clock domain + hsD <= hs_in; + hsD2 <= hsD; + + // falling edge of hs_in + if(!hsD && hsD2) begin + h_cnt <= 10'd0; + hs_high <= h_cnt; + end + + // rising edge of hs_in + else if(hsD && !hsD2) begin + h_cnt <= 10'd0; + hs_low <= h_cnt; + end + + else + h_cnt <= h_cnt + 10'd1; +end + +// vertical counter +reg [9:0] v_cnt; +reg vsD, vsD2; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high; +wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] }; + +always @(posedge hs_in) begin + // bring vsync into local clock domain + vsD <= vs_in; + vsD2 <= vsD; + + // falling edge of vs_in + if(!vsD && vsD2) begin + v_cnt <= 10'd0; + vs_high <= v_cnt; + end + + // rising edge of vs_in + else if(vsD && !vsD2) begin + v_cnt <= 10'd0; + vs_low <= v_cnt; + end + + else + v_cnt <= v_cnt + 10'd1; +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1); +wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1; +wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1); +wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1; + +reg h_osd_active, v_osd_active; +always @(posedge pclk) begin + if(hs_in != hs_pol) begin + if(h_cnt == h_osd_start) h_osd_active <= 1'b1; + if(h_cnt == h_osd_end) h_osd_active <= 1'b0; + end + if(vs_in != vs_pol) begin + if(v_cnt == v_osd_start) v_osd_active <= 1'b1; + if(v_cnt == v_osd_end) v_osd_active <= 1'b0; + end +end + +wire osd_de = osd_enable && h_osd_active && v_osd_active; + +wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register +wire [6:0] osd_vcnt = v_cnt - v_osd_start; + +wire osd_pixel = osd_byte[osd_vcnt[3:1]]; + +reg [7:0] osd_byte; +always @(posedge pclk) + osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}]; + +wire [2:0] osd_color = OSD_COLOR; +assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] }; +assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]}; +assign blue_out = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] }; + +assign hs_out = hs_in; +assign vs_out = vs_in; + +endmodule \ No newline at end of file diff --git a/Board/mist/sd_card.v b/Board/mist/sd_card.v new file mode 100644 index 0000000..70d3852 --- /dev/null +++ b/Board/mist/sd_card.v @@ -0,0 +1,468 @@ +// +// sd_card.v +// +// This file implelents a sd card for the MIST board since on the board +// the SD card is connected to the ARM IO controller and the FPGA has no +// direct connection to the SD card. This file provides a SD card like +// interface to the IO controller easing porting of cores that expect +// a direct interface to the SD card. +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// http://elm-chan.org/docs/mmc/mmc_e.html + +// TODO: +// - CMD9: SEND_CSD (requires device capacity) +// - CMD10: SEND_CID + +module sd_card ( + // link to user_io for io controller + output [31:0] io_lba, + output reg io_rd, + output reg io_wr, + input io_ack, + output io_conf, + output io_sdhc, + + // data coming in from io controller + input [7:0] io_din, + input io_din_strobe, + + // data going out to io controller + output [7:0] io_dout, + input io_dout_strobe, + + // configuration input + input allow_sdhc, + + input sd_cs, + input sd_sck, + input sd_sdi, + output reg sd_sdo +); + +// set io_rd once read_state machine starts waiting (rising edge of req_io_rd) +// and clear it once io controller uploads something (io_ack==1) +wire req_io_rd = (read_state == 3'd1); +wire io_reset = io_ack || sd_cs; +always @(posedge req_io_rd or posedge io_reset) begin + if(io_reset) io_rd <= 1'b0; + else io_rd <= 1'b1; +end + +wire req_io_wr = (write_state == 3'd6); +always @(posedge req_io_wr or posedge io_reset) begin + if(io_reset) io_wr <= 1'b0; + else io_wr <= 1'b1; +end + +// set io_read_ack on falling edge of io_ack +// reset it when not waiting for io controller (anymore) +reg io_read_ack; +wire io_read_wait_io = (read_state == 1); +always @(negedge io_ack or negedge io_read_wait_io) begin + if(!io_read_wait_io) io_read_ack <= 1'b0; + else io_read_ack <= 1'b1; +end + +// set io_write_ack on falling edge of io_ack +// reset it when not waiting for io controller (anymore) +reg io_write_ack; +wire io_write_wait_io = (write_state == 6); +always @(negedge io_ack or negedge io_write_wait_io) begin + if(!io_write_wait_io) io_write_ack <= 1'b0; + else io_write_ack <= 1'b1; +end + +wire [31:0] OCR = { 1'b0, io_sdhc, 30'h0 }; // bit30 = 1 -> high capaciry card (sdhc) +wire [7:0] READ_DATA_TOKEN = 8'hfe; + +localparam NCR=4; + +// 0=idle, 1=wait for io ctrl, 2=wait for byte start, 2=send token, 3=send data, 4/5=send crc[0..1] +reg [2:0] read_state; + +// 0=idle +reg [2:0] write_state; + +reg [6:0] sbuf; +reg cmd55; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [7:0] byte_cnt; // counts bytes, saturates at 255 +reg [7:0] cmd_cnt; // counts command bytes, returns to 0 after last command byte + +reg [7:0] lba0, lba1, lba2, lba3; +assign io_lba = io_sdhc?{ lba3, lba2, lba1, lba0 }:{9'd0, lba3, lba2, lba1[7:1]}; + +// the command crc is actually never evaluated +reg [7:0] crc; + +reg [7:0] reply; +reg [7:0] reply0, reply1, reply2, reply3; +reg [3:0] reply_len; + +// signals to address buffer on SD card write (data coming from SD spi) +reg write_strobe; +reg [7:0] write_data; + +// ------------------------- SECTOR BUFFER ----------------------- + +// access to the sector buffer is multiplexed. When reading sectors +// the io controller writes into the buffer and the sd card implementation +// reads. And vice versa when writing sectors +wire reading = (read_state != 0); +wire writing = (write_state != 0); + +// the buffer itself. Can hold one sector +reg [8:0] buffer_wptr; +reg [8:0] buffer_rptr; +reg [7:0] buffer [511:0]; +reg [7:0] buffer_byte; + +// ---------------- buffer read engine ----------------------- +reg core_buffer_read_strobe; +wire buffer_read_latch = reading?sd_sck:io_dout_strobe; +wire buffer_read_strobe = reading?core_buffer_read_strobe:!io_dout_strobe; +assign io_dout = buffer_byte; + +// sdo is sampled on negative sd clock so set it on positive edge +always @(posedge buffer_read_latch) + buffer_byte <= buffer[buffer_rptr]; + +always @(posedge buffer_read_strobe or posedge sd_cs) begin + if(sd_cs == 1) buffer_rptr <= 9'd0; + else buffer_rptr <= buffer_rptr + 9'd1; +end + +// ---------------- buffer write engine ----------------------- +wire [7:0] buffer_din = reading?io_din:write_data; +wire buffer_din_strobe = reading?io_din_strobe:write_strobe; + +always @(negedge buffer_din_strobe or posedge sd_cs) begin + if(sd_cs == 1) begin + buffer_wptr <= 9'd0; + end else begin + buffer[buffer_wptr] <= buffer_din; + buffer_wptr <= buffer_wptr + 9'd1; + end +end + +wire [7:0] WRITE_DATA_RESPONSE = 8'h05; + +// ------------------------- CSD/CID BUFFER ---------------------- +assign io_conf = (csd_wptr == 0); + +// the 32 bytes as sent from the io controller +reg [7:0] cid [15:0]; +reg [7:0] csd [15:0]; +reg [7:0] conf; + +reg [7:0] cid_byte; +reg [7:0] csd_byte; +reg [5:0] csd_wptr = 6'd0; + +// conf[0]==1 -> io controller is using an sdhc card +wire io_has_sdhc = conf[0]; +assign io_sdhc = allow_sdhc && io_has_sdhc; + +always @(negedge io_din_strobe) begin + // if io controller sends data without asserting io_ack, then it's + // updating the config + if(!io_ack && (csd_wptr <= 32)) begin + + if(csd_wptr < 16) // first 16 bytes are cid + cid[csd_wptr] <= io_din; + if((csd_wptr >= 16) && (csd_wptr < 32)) // then comes csd + csd[csd_wptr-16] <= io_din; + if(csd_wptr == 32) // finally a config byte + conf <= io_din; + + csd_wptr <= csd_wptr + 1; + end +end + +always @(posedge buffer_read_latch) + cid_byte <= cid[buffer_rptr]; + +always @(posedge buffer_read_latch) + csd_byte <= csd[buffer_rptr]; + + +// ----------------- spi transmitter -------------------- +always@(negedge sd_sck or posedge sd_cs) begin + if(sd_cs == 1) begin + sd_sdo <= 1'b1; + read_state <= 3'd0; + end else begin + core_buffer_read_strobe <= 1'b0; + + // -------- catch read commmand and reset read state machine ------ + if(bit_cnt == 7) begin + if(cmd_cnt == 5) begin + // CMD17: READ_SINGLE_BLOCK + if(cmd == 8'h51) + read_state <= 3'd1; // start waiting for data from io controller + end + end + + if(byte_cnt < 6+NCR) begin + sd_sdo <= 1'b1; // reply $ff -> wait + end else begin + + if(byte_cnt == 6+NCR) begin + sd_sdo <= reply[~bit_cnt]; + + if(bit_cnt == 7) begin + // CMD9: SEND_CSD + // CMD10: SEND_CID + if((cmd == 8'h49)||(cmd == 8'h4a)) + read_state <= 3'd3; // jump directly to data transmission + end + end else if((reply_len > 0) && (byte_cnt == 6+NCR+1)) + sd_sdo <= reply0[~bit_cnt]; + else if((reply_len > 1) && (byte_cnt == 6+NCR+2)) + sd_sdo <= reply1[~bit_cnt]; + else if((reply_len > 2) && (byte_cnt == 6+NCR+3)) + sd_sdo <= reply2[~bit_cnt]; + else if((reply_len > 3) && (byte_cnt == 6+NCR+4)) + sd_sdo <= reply3[~bit_cnt]; + else + sd_sdo <= 1'b1; + + // falling edge of io_ack signals end of incoming data stream + if((read_state == 3'd1) && io_read_ack) + read_state <= 3'd2; + + // wait for begin of new byte + if((read_state == 3'd2) && (bit_cnt == 7)) + read_state <= 3'd3; + + // send data token + if(read_state == 3'd3) begin + sd_sdo <= READ_DATA_TOKEN[~bit_cnt]; + + if(bit_cnt == 7) + read_state <= 3'd4; // next: send data + end + + // send data + if(read_state == 3'd4) begin + if(cmd == 8'h51) // CMD17: READ_SINGLE_BLOCK + sd_sdo <= buffer_byte[~bit_cnt]; + else if(cmd == 8'h49) // CMD9: SEND_CSD + sd_sdo <= csd_byte[~bit_cnt]; + else if(cmd == 8'h4a) // CMD10: SEND_CID + sd_sdo <= cid_byte[~bit_cnt]; + + if(bit_cnt == 7) begin + core_buffer_read_strobe <= 1'b1; + + // send 512 sector data bytes? + if((cmd == 8'h51) && (buffer_rptr == 511)) + read_state <= 3'd5; // next: send crc + + // send 16 cid/csd data bytes? + if(((cmd == 8'h49)||(cmd == 8'h4a)) && (buffer_rptr == 15)) + read_state <= 3'd0; // return to idle state + end + end + + // send crc[0] + if(read_state == 3'd5) begin + sd_sdo <= 1'b1; + if(bit_cnt == 7) + read_state <= 3'd6; // send second crc byte + end + + // send crc[1] + if(read_state == 3'd6) begin + sd_sdo <= 1'b1; + if(bit_cnt == 7) + read_state <= 3'd0; // return to idle state + end + + // send write data response + if(write_state == 3'd5) + sd_sdo <= WRITE_DATA_RESPONSE[~bit_cnt]; + + // busy after write until the io controller sends ack + if(write_state == 3'd6) + sd_sdo <= 1'b0; + end + end +end + +// spi receiver +always @(posedge sd_sck or posedge sd_cs) begin + // cs is active low + if(sd_cs == 1) begin + bit_cnt <= 3'd0; + byte_cnt <= 8'd0; + cmd_cnt <= 8'd0; + write_state <= 3'd0; + write_strobe <= 1'b0; + end else begin + write_strobe <= 1'b0; + sbuf[6:0] <= { sbuf[5:0], sd_sdi }; + bit_cnt <= bit_cnt + 3'd1; + + if((bit_cnt == 7)&&(byte_cnt != 255)) begin + byte_cnt <= byte_cnt + 8'd1; + + if(cmd_cnt == 0) begin + // first byte of valid command is 01xxxxxx + if((write_state == 3'd0) && sbuf[6:5] == 2'b01) begin + cmd_cnt <= 8'd1; + byte_cnt <= 8'd1; + end + end else if(cmd_cnt < 6) + cmd_cnt <= cmd_cnt + 8'd1; + else + // command counting stops after last command byte. + cmd_cnt <= 8'd0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + + // don't accept new commands once a write command has been accepted + if((write_state == 3'd0) && (cmd_cnt == 0)&&(sbuf[6:5] == 2'b01)) begin + cmd <= { sbuf, sd_sdi}; + + // set cmd55 flag if previous command was 55 + cmd55 <= (cmd == 8'h77); + end + + // parse additional command bytes + if(cmd_cnt == 1) lba3 <= { sbuf, sd_sdi}; + if(cmd_cnt == 2) lba2 <= { sbuf, sd_sdi}; + if(cmd_cnt == 3) lba1 <= { sbuf, sd_sdi}; + if(cmd_cnt == 4) lba0 <= { sbuf, sd_sdi}; + if(cmd_cnt == 5) crc <= { sbuf, sd_sdi}; + + // last byte received, evaluate + if(cmd_cnt == 5) begin + // default: + reply <= 8'h04; // illegal command + reply_len <= 4'd0; // no extra reply bytes + + + // CMD0: GO_IDLE_STATE + if(cmd == 8'h40) + reply <= 8'h01; // ok, busy + + // CMD1: SEND_OP_COND + else if(cmd == 8'h41) + reply <= 8'h00; // ok, not busy + + // CMD8: SEND_IF_COND (V2 only) + else if(cmd == 8'h48) begin + reply <= 8'h01; // ok, busy + reply0 <= 8'h00; + reply1 <= 8'h00; + reply2 <= 8'h01; + reply3 <= 8'hAA; + reply_len <= 4'd4; + end + + // CMD9: SEND_CSD + else if(cmd == 8'h49) + reply <= 8'h00; // ok + + // CMD10: SEND_CID + else if(cmd == 8'h4a) + reply <= 8'h00; // ok + + // CMD16: SET_BLOCKLEN + else if(cmd == 8'h50) begin + // we only support a block size of 512 + if(io_lba == 32'd512) + reply <= 8'h00; // ok + else + reply <= 8'h40; // parmeter error + end + + // CMD17: READ_SINGLE_BLOCK + else if(cmd == 8'h51) + reply <= 8'h00; // ok + + // CMD24: WRITE_BLOCK + else if(cmd == 8'h58) begin + reply <= 8'h00; // ok + write_state <= 3'd1; // expect data token + end + + // ACMD41: APP_SEND_OP_COND + else if(cmd55 && (cmd == 8'h69)) + reply <= 8'h00; // ok, not busy + + // CMD55: APP_COND + else if(cmd == 8'h77) + reply <= 8'h01; // ok, busy + + // CMD58: READ_OCR + else if(cmd == 8'h7a) begin + reply <= 8'h00; // ok + + reply0 <= OCR[31:24]; // bit 30 = 1 -> high capacity card + reply1 <= OCR[23:16]; + reply2 <= OCR[15:8]; + reply3 <= OCR[7:0]; + reply_len <= 4'd4; + end + end + + // ---------- handle write ----------- + + // waiting for data token + if(write_state == 3'd1) begin + if({ sbuf, sd_sdi} == 8'hfe ) + write_state <= 3'd2; + end + + // transfer 512 bytes + if(write_state == 3'd2) begin + // push one byte into local buffer + write_strobe <= 1'b1; + write_data <= { sbuf, sd_sdi}; + + if(buffer_wptr == 511) + write_state <= 3'd3; + end + + // transfer 1st crc byte + if(write_state == 3'd3) + write_state <= 3'd4; + + // transfer 2nd crc byte + if(write_state == 3'd4) + write_state <= 3'd5; + + // send data response + if(write_state == 3'd5) + write_state <= 3'd6; + end + + // wait for io controller to accept data + // this happens outside the bit_cnt == 7 test as the + // transition may happen at any time + if(write_state == 3'd6 && io_write_ack) + write_state <= 3'd0; + end +end + +endmodule diff --git a/Board/mist/user_io.v b/Board/mist/user_io.v new file mode 100644 index 0000000..10c8d57 --- /dev/null +++ b/Board/mist/user_io.v @@ -0,0 +1,409 @@ +// +// user_io.v +// +// user_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +// parameter STRLEN and the actual length of conf_str have to match + +module user_io #(parameter STRLEN=0) ( + input [(8*STRLEN)-1:0] conf_str, + + input SPI_CLK, + input SPI_SS_IO, + output reg SPI_MISO, + input SPI_MOSI, + + output reg [5:0] joystick_0, + output reg [5:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + + output reg [7:0] status, + + // connection to sd card emulation + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + input sd_conf, + input sd_sdhc, + output reg [7:0] sd_dout, + output reg sd_dout_strobe, + input [7:0] sd_din, + output reg sd_din_strobe, + + + // ps2 keyboard emulation + input ps2_clk, // 12-16khz provided by core + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + + // serial com port + input [7:0] serial_data, + input serial_strobe +); + +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [7:0] byte_cnt; // counts bytes +reg [5:0] joystick0; +reg [5:0] joystick1; +reg [3:0] but_sw; +reg [2:0] stick_idx; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +// filter spi clock. the 8 bit gate delay is ~2.5ns in total +wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */; +wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff); + +// drive MISO only when transmitting core id +always@(negedge spi_sck or posedge SPI_SS_IO) begin + if(SPI_SS_IO == 1) begin + SPI_MISO <= 1'bZ; + end else begin + + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + SPI_MISO <= core_type[~bit_cnt]; + + end else begin + // reading serial fifo + if(cmd == 8'h1b) begin + // send alternating flag byte and data + if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt]; + else SPI_MISO <= serial_out_byte[~bit_cnt]; + end + + // reading config string + else if(cmd == 8'h14) begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) + SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else + SPI_MISO <= 1'b0; + end + + // reading sd card status + else if(cmd == 8'h16) begin + if(byte_cnt == 1) + SPI_MISO <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) + SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else + SPI_MISO <= 1'b0; + end + + // reading sd card write data + else if(cmd == 8'h18) + SPI_MISO <= sd_din[~bit_cnt]; + + else + SPI_MISO <= 1'b0; + end + end +end + +// ---------------- PS2 --------------------- + +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +// keyboard +reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0]; +reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr; +reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr; + +// ps2 transmitter state machine +reg [3:0] ps2_kbd_tx_state; +reg [7:0] ps2_kbd_tx_byte; +reg ps2_kbd_parity; + +assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0); + +// ps2 transmitter +// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. +reg ps2_kbd_r_inc; +always@(posedge ps2_clk) begin + ps2_kbd_r_inc <= 1'b0; + + if(ps2_kbd_r_inc) + ps2_kbd_rptr <= ps2_kbd_rptr + 1; + + // transmitter is idle? + if(ps2_kbd_tx_state == 0) begin + // data in fifo present? + if(ps2_kbd_wptr != ps2_kbd_rptr) begin + // load tx register from fifo + ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr]; + ps2_kbd_r_inc <= 1'b1; + + // reset parity + ps2_kbd_parity <= 1'b1; + + // start transmitter + ps2_kbd_tx_state <= 4'd1; + + // put start bit on data line + ps2_kbd_data <= 1'b0; // start bit is 0 + end + end else begin + + // transmission of 8 data bits + if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) + ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) + ps2_kbd_data <= 1'b1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) + ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1; + else + ps2_kbd_tx_state <= 4'd0; + + end +end + +// mouse +reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0]; +reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr; +reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr; + +// ps2 transmitter state machine +reg [3:0] ps2_mouse_tx_state; +reg [7:0] ps2_mouse_tx_byte; +reg ps2_mouse_parity; + +assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0); + +// ps2 transmitter +// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. +reg ps2_mouse_r_inc; +always@(posedge ps2_clk) begin + ps2_mouse_r_inc <= 1'b0; + + if(ps2_mouse_r_inc) + ps2_mouse_rptr <= ps2_mouse_rptr + 1; + + // transmitter is idle? + if(ps2_mouse_tx_state == 0) begin + // data in fifo present? + if(ps2_mouse_wptr != ps2_mouse_rptr) begin + // load tx register from fifo + ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr]; + ps2_mouse_r_inc <= 1'b1; + + // reset parity + ps2_mouse_parity <= 1'b1; + + // start transmitter + ps2_mouse_tx_state <= 4'd1; + + // put start bit on data line + ps2_mouse_data <= 1'b0; // start bit is 0 + end + end else begin + + // transmission of 8 data bits + if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) + ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) + ps2_mouse_data <= 1'b1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) + ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1; + else + ps2_mouse_tx_state <= 4'd0; + + end +end + +// fifo to receive serial data from core to be forwarded to io controller + +// 16 byte fifo to store serial bytes +localparam SERIAL_OUT_FIFO_BITS = 6; +reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0]; +reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr; +reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr; + +wire serial_out_data_available = serial_out_wptr != serial_out_rptr; +wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */; +wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available}; + +// status[0] is reset signal from io controller and is thus used to flush +// the fifo +always @(posedge serial_strobe or posedge status[0]) begin + if(status[0] == 1) begin + serial_out_wptr <= 0; + end else begin + serial_out_fifo[serial_out_wptr] <= serial_data; + serial_out_wptr <= serial_out_wptr + 1; + end +end + +always@(negedge spi_sck or posedge status[0]) begin + if(status[0] == 1) begin + serial_out_rptr <= 0; + end else begin + if((byte_cnt != 0) && (cmd == 8'h1b)) begin + // read last bit -> advance read pointer + if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available) + serial_out_rptr <= serial_out_rptr + 1; + end + end +end + +// SPI receiver +always@(posedge spi_sck or posedge SPI_SS_IO) begin + + if(SPI_SS_IO == 1) begin + bit_cnt <= 3'd0; + byte_cnt <= 8'd0; + sd_ack <= 1'b0; + sd_dout_strobe <= 1'b0; + sd_din_strobe <= 1'b0; + end else begin + sd_dout_strobe <= 1'b0; + sd_din_strobe <= 1'b0; + + sbuf[6:0] <= { sbuf[5:0], SPI_MOSI }; + bit_cnt <= bit_cnt + 3'd1; + if((bit_cnt == 7)&&(byte_cnt != 8'd255)) + byte_cnt <= byte_cnt + 8'd1; + + // finished reading command byte + if(bit_cnt == 7) begin + if(byte_cnt == 0) begin + cmd <= { sbuf, SPI_MOSI}; + + // fetch first byte when sectore FPGA->IO command has been seen + if({ sbuf, SPI_MOSI} == 8'h18) + sd_din_strobe <= 1'b1; + + if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18)) + sd_ack <= 1'b1; + + end else begin + + // buttons and switches + if(cmd == 8'h01) + but_sw <= { sbuf[2:0], SPI_MOSI }; + + if(cmd == 8'h02) + joystick_0 <= { sbuf[4:0], SPI_MOSI }; + + if(cmd == 8'h03) + joystick_1 <= { sbuf[4:0], SPI_MOSI }; + + if(cmd == 8'h04) begin + // store incoming ps2 mouse bytes + ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI }; + ps2_mouse_wptr <= ps2_mouse_wptr + 1; + end + + if(cmd == 8'h05) begin + // store incoming ps2 keyboard bytes + ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI }; + ps2_kbd_wptr <= ps2_kbd_wptr + 1; + end + + if(cmd == 8'h15) + status <= { sbuf[6:0], SPI_MOSI }; + + // send sector IO -> FPGA + if(cmd == 8'h17) begin + // flag that download begins + sd_dout <= { sbuf, SPI_MOSI}; + sd_dout_strobe <= 1'b1; + end + + // send sector FPGA -> IO + if(cmd == 8'h18) + sd_din_strobe <= 1'b1; + + // send SD config IO -> FPGA + if(cmd == 8'h19) begin + // flag that download begins + sd_dout <= { sbuf, SPI_MOSI}; + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + sd_dout_strobe <= 1'b1; + end + + // joystick analog + if(cmd == 8'h1a) begin + // first byte is joystick indes + if(byte_cnt == 1) + stick_idx <= { sbuf[1:0], SPI_MOSI }; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) + joystick_analog_0[15:8] <= { sbuf, SPI_MOSI }; + else if(stick_idx == 1) + joystick_analog_1[15:8] <= { sbuf, SPI_MOSI }; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) + joystick_analog_0[7:0] <= { sbuf, SPI_MOSI }; + else if(stick_idx == 1) + joystick_analog_1[7:0] <= { sbuf, SPI_MOSI }; + end + end + + end + end + end +end + +endmodule diff --git a/SOC/fpga/ems11-bb37/EMS11_BB30Toplevel_bitgen.xwbt b/SOC/fpga/ems11-bb37/EMS11_BB30Toplevel_bitgen.xwbt new file mode 100644 index 0000000..2cef550 --- /dev/null +++ b/SOC/fpga/ems11-bb37/EMS11_BB30Toplevel_bitgen.xwbt @@ -0,0 +1,8 @@ +INTSTYLE=ise +INFILE=D:\_home\emu\_User\Alastair-M-Robinson\GitHub\TG68_MiniSOC.git\branches\master\SOC\fpga\ems11-bb37\EMS11_BB30Toplevel.ncd +OUTFILE=D:\_home\emu\_User\Alastair-M-Robinson\GitHub\TG68_MiniSOC.git\branches\master\SOC\fpga\ems11-bb37\EMS11_BB30Toplevel.bit +FAMILY=Spartan6 +PART=xc6slx45-3fgg676 +WORKINGDIR=D:\_home\emu\_User\Alastair-M-Robinson\GitHub\TG68_MiniSOC.git\branches\master\SOC\fpga\ems11-bb37 +LICENSE=WebPack +USER_INFO=174126493_174126494_0_251 diff --git a/SOC/fpga/ems11-bb37/SOC.gise b/SOC/fpga/ems11-bb37/SOC.gise new file mode 100644 index 0000000..d584ff3 --- /dev/null +++ b/SOC/fpga/ems11-bb37/SOC.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/SOC/fpga/ems11-bb37/SOC.xise b/SOC/fpga/ems11-bb37/SOC.xise new file mode 100644 index 0000000..d195b15 --- /dev/null +++ b/SOC/fpga/ems11-bb37/SOC.xise @@ -0,0 +1,506 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SOC/fpga/ems11-bb37/abb_tb.vhd b/SOC/fpga/ems11-bb37/abb_tb.vhd new file mode 100644 index 0000000..87be574 --- /dev/null +++ b/SOC/fpga/ems11-bb37/abb_tb.vhd @@ -0,0 +1,191 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:20:35 05/20/2014 +-- Design Name: +-- Module Name: C:/Users/CHEMSTI/HOME/TG68_MiniSOC/branches/burst8/SOC/fpga/ems11-bb21/abb_tb.vhd +-- Project Name: SOC +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: EMS11_BB21Toplevel +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY abb_tb IS +END abb_tb; + +ARCHITECTURE behavior OF abb_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT EMS11_BB21Toplevel + PORT( + CLK50 : IN std_logic; + UART1_TXD : OUT std_logic; + UART1_RXD : IN std_logic; + UART1_RTS_N : OUT std_logic; + UART1_CTS_N : IN std_logic; + DR_CAS_N : OUT std_logic; + DR_CS_N : OUT std_logic; + DR_RAS_N : OUT std_logic; + DR_WE_N : OUT std_logic; + DR_CLK_I : IN std_logic; + DR_CLK_O : OUT std_logic; + DR_CKE : OUT std_logic; + DR_A : OUT std_logic_vector(12 downto 0); + DR_D : INOUT std_logic_vector(15 downto 0); + DR_DQMH : OUT std_logic; + DR_DQML : OUT std_logic; + DR_BA : OUT std_logic_vector(1 downto 0); + FPGA_SD_CDET_N : IN std_logic; + FPGA_SD_WPROT_N : IN std_logic; + FPGA_SD_CMD : OUT std_logic; + FPGA_SD_D0 : IN std_logic; + FPGA_SD_D1 : IN std_logic; + FPGA_SD_D2 : IN std_logic; + FPGA_SD_D3 : OUT std_logic; + FPGA_SD_SCLK : OUT std_logic; + UART2_RTS_N : OUT std_logic; + M1_S : INOUT std_logic_vector(39 downto 0); + LED1 : OUT std_logic; + LED2 : OUT std_logic; + GPIO : INOUT std_logic_vector(15 downto 0); + DIAG_N : IN std_logic; + RESET_N : IN std_logic + ); + END COMPONENT; + + + --Inputs + signal CLK50 : std_logic := '0'; + signal UART1_RXD : std_logic := '0'; + signal UART1_CTS_N : std_logic := '0'; + signal DR_CLK_I : std_logic := '0'; + signal FPGA_SD_CDET_N : std_logic := '0'; + signal FPGA_SD_WPROT_N : std_logic := '0'; + signal FPGA_SD_D0 : std_logic := '0'; + signal FPGA_SD_D1 : std_logic := '0'; + signal FPGA_SD_D2 : std_logic := '0'; + signal DIAG_N : std_logic := '0'; + signal RESET_N : std_logic := '0'; + + --BiDirs + signal DR_D : std_logic_vector(15 downto 0); + signal M1_S : std_logic_vector(39 downto 0); + signal GPIO : std_logic_vector(15 downto 0); + + --Outputs + signal UART1_TXD : std_logic; + signal UART1_RTS_N : std_logic; + signal DR_CAS_N : std_logic; + signal DR_CS_N : std_logic; + signal DR_RAS_N : std_logic; + signal DR_WE_N : std_logic; + signal DR_CLK_O : std_logic; + signal DR_CKE : std_logic; + signal DR_A : std_logic_vector(12 downto 0); + signal DR_DQMH : std_logic; + signal DR_DQML : std_logic; + signal DR_BA : std_logic_vector(1 downto 0); + signal FPGA_SD_CMD : std_logic; + signal FPGA_SD_D3 : std_logic; + signal FPGA_SD_SCLK : std_logic; + signal UART2_RTS_N : std_logic; + signal LED1 : std_logic; + signal LED2 : std_logic; + + -- Clock period definitions + constant CLK50_period : time := 10 ns; + constant FPGA_SD_SCLK_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: EMS11_BB21Toplevel PORT MAP ( + CLK50 => CLK50, + UART1_TXD => UART1_TXD, + UART1_RXD => UART1_RXD, + UART1_RTS_N => UART1_RTS_N, + UART1_CTS_N => UART1_CTS_N, + DR_CAS_N => DR_CAS_N, + DR_CS_N => DR_CS_N, + DR_RAS_N => DR_RAS_N, + DR_WE_N => DR_WE_N, + DR_CLK_I => DR_CLK_I, + DR_CLK_O => DR_CLK_O, + DR_CKE => DR_CKE, + DR_A => DR_A, + DR_D => DR_D, + DR_DQMH => DR_DQMH, + DR_DQML => DR_DQML, + DR_BA => DR_BA, + FPGA_SD_CDET_N => FPGA_SD_CDET_N, + FPGA_SD_WPROT_N => FPGA_SD_WPROT_N, + FPGA_SD_CMD => FPGA_SD_CMD, + FPGA_SD_D0 => FPGA_SD_D0, + FPGA_SD_D1 => FPGA_SD_D1, + FPGA_SD_D2 => FPGA_SD_D2, + FPGA_SD_D3 => FPGA_SD_D3, + FPGA_SD_SCLK => FPGA_SD_SCLK, + UART2_RTS_N => UART2_RTS_N, + M1_S => M1_S, + LED1 => LED1, + LED2 => LED2, + GPIO => GPIO, + DIAG_N => DIAG_N, + RESET_N => RESET_N + ); + + -- Clock process definitions + CLK50_process :process + begin + CLK50 <= '0'; + wait for CLK50_period/2; + CLK50 <= '1'; + wait for CLK50_period/2; + end process; + + FPGA_SD_SCLK_process :process + begin + FPGA_SD_SCLK <= '0'; + wait for FPGA_SD_SCLK_period/2; + FPGA_SD_SCLK <= '1'; + wait for FPGA_SD_SCLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 100 ns; + RESET_N <= '0'; + wait for CLK50_period*10; + RESET_N <= '1'; + -- insert stimulus here + + wait; + end process; + +END; diff --git a/SOC/fpga/ems11-bb37/abb_tb.wcfg b/SOC/fpga/ems11-bb37/abb_tb.wcfg new file mode 100644 index 0000000..c6fad06 --- /dev/null +++ b/SOC/fpga/ems11-bb37/abb_tb.wcfg @@ -0,0 +1,172 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clk50 + clk50 + + + uart1_rxd + uart1_rxd + + + uart1_cts_n + uart1_cts_n + + + dr_clk_i + dr_clk_i + + + fpga_sd_cdet_n + fpga_sd_cdet_n + + + fpga_sd_wprot_n + fpga_sd_wprot_n + + + fpga_sd_d0 + fpga_sd_d0 + + + fpga_sd_d1 + fpga_sd_d1 + + + fpga_sd_d2 + fpga_sd_d2 + + + diag_n + diag_n + + + reset_n + reset_n + + + dr_d[15:0] + dr_d[15:0] + + + m1_s[39:0] + m1_s[39:0] + + + gpio[15:0] + gpio[15:0] + + + uart1_txd + uart1_txd + + + uart1_rts_n + uart1_rts_n + + + dr_cas_n + dr_cas_n + + + dr_cs_n + dr_cs_n + + + dr_ras_n + dr_ras_n + + + dr_we_n + dr_we_n + + + dr_clk_o + dr_clk_o + + + dr_cke + dr_cke + + + dr_a[12:0] + dr_a[12:0] + + + dr_dqmh + dr_dqmh + + + dr_dqml + dr_dqml + + + dr_ba[1:0] + dr_ba[1:0] + + + fpga_sd_cmd + fpga_sd_cmd + + + fpga_sd_d3 + fpga_sd_d3 + + + fpga_sd_sclk + fpga_sd_sclk + + + uart2_rts_n + uart2_rts_n + + + led1 + led1 + + + led2 + led2 + + + clk50_period + clk50_period + + + fpga_sd_sclk_period + fpga_sd_sclk_period + + + gpio_dir[15:0] + gpio_dir[15:0] + + + gpio_data[15:0] + gpio_data[15:0] + + diff --git a/SOC/fpga/ems11-bb37/impact.xsl b/SOC/fpga/ems11-bb37/impact.xsl new file mode 100644 index 0000000..e4999d7 --- /dev/null +++ b/SOC/fpga/ems11-bb37/impact.xsl @@ -0,0 +1,55 @@ + + + + + + + Current iMPACT Usage Statistics. +

+ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. + +

+

+ This page displays the current iMPACT device usage statistics that will be sent to Xilinx using WebTalk. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + diff --git a/SOC/fpga/ems11-bb37/impact_impact.xwbt b/SOC/fpga/ems11-bb37/impact_impact.xwbt new file mode 100644 index 0000000..be46a53 --- /dev/null +++ b/SOC/fpga/ems11-bb37/impact_impact.xwbt @@ -0,0 +1,8 @@ +INTSTYLE=impact +INFILE=D:\_home\emu\_User\Alastair-M-Robinson\GitHub\TG68_MiniSOC\branches\burst8\SOC\fpga\ems11-bb21\impact.xsl +OUTFILE=D:\_home\emu\_User\Alastair-M-Robinson\GitHub\TG68_MiniSOC\branches\burst8\SOC\fpga\ems11-bb21\impact.xsl +FAMILY=Single +PART=Single +WORKINGDIR=D:\_home\emu\_User\Alastair-M-Robinson\GitHub\TG68_MiniSOC\branches\burst8\SOC\fpga\ems11-bb21 +LICENSE=iMPACT +USER_INFO=iMPACT diff --git a/SOC/fpga/ems11-bb37/iseconfig/EMS11_BB21Toplevel.xreport b/SOC/fpga/ems11-bb37/iseconfig/EMS11_BB21Toplevel.xreport new file mode 100644 index 0000000..d630906 --- /dev/null +++ b/SOC/fpga/ems11-bb37/iseconfig/EMS11_BB21Toplevel.xreport @@ -0,0 +1,215 @@ + + +
+ 2014-06-10T14:17:09 + EMS11_BB30Toplevel + 2014-06-10T14:05:50 + C:/Users/CHEMSTI/HOME/TG68_MiniSOC.EMU/branches/burst8/SOC/fpga/ems11-bb30-new/iseconfig/EMS11_BB21Toplevel.xreport + C:/Users/CHEMSTI/HOME/TG68_MiniSOC.EMU/branches/burst8/SOC/fpga/ems11-bb30-new\ + 2014-06-10T12:31:19 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SOC/fpga/ems11-bb37/iseconfig/EMS11_BB30Toplevel.xreport b/SOC/fpga/ems11-bb37/iseconfig/EMS11_BB30Toplevel.xreport new file mode 100644 index 0000000..83362da --- /dev/null +++ b/SOC/fpga/ems11-bb37/iseconfig/EMS11_BB30Toplevel.xreport @@ -0,0 +1,215 @@ + + +
+ 2014-10-02T09:08:51 + EMS11_BB30Toplevel + 2014-08-14T10:45:11 + D:/_home/emu/_User/Alastair-M-Robinson/GitHub/TG68_MiniSOC.git/branches/master/SOC/fpga/ems11-bb37/iseconfig/EMS11_BB30Toplevel.xreport + D:/_home/emu/_User/Alastair-M-Robinson/GitHub/TG68_MiniSOC.git/branches/master/SOC/fpga/ems11-bb37\ + 2014-08-14T10:32:15 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SOC/fpga/ems11-bb37/iseconfig/SOC.projectmgr b/SOC/fpga/ems11-bb37/iseconfig/SOC.projectmgr new file mode 100644 index 0000000..8ee5900 --- /dev/null +++ b/SOC/fpga/ems11-bb37/iseconfig/SOC.projectmgr @@ -0,0 +1,253 @@ + + + + + + + + + 2 + /DMACache - rtl |home|amr|FPGA|TG68MiniSOC|RTL|Memory|DMACache.vhd + /EMS11_BB21Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC.EMU|branches|burst8|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl + /EMS11_BB21Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC.EMU|branches|burst8|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/myTG68 - TG68KdotC_Kernel - logic + /EMS11_BB21Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC.EMU|branches|burst8|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/myaudio - sound_wrapper - rtl + /EMS11_BB21Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC.EMU|branches|burst8|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/mydmacache - DMACache - rtl + /EMS11_BB21Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC.EMU|branches|burst8|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/myperipheral - peripheral_controller - rtl + /EMS11_BB21Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC.EMU|branches|burst8|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/mysdram - sdram - rtl + /EMS11_BB21Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC.EMU|branches|burst8|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/myvga - vga_controller - rtl + /EMS11_BB21Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC.EMU|branches|burst8|Board|ems11-bb21|EMS11_BB30Toplevel.vhd/project - VirtualToplevel - rtl + /EMS11_BB21Toplevel - rtl |home|amr|FPGA|TG68MiniSOC|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/myTG68 - TG68KdotC_Kernel - logic + /EMS11_BB21Toplevel - rtl |home|amr|FPGA|TG68MiniSOC|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/myperipheral - peripheral_controller - rtl + /EMS11_BB21Toplevel - rtl |home|amr|FPGA|TG68MiniSOC|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/mysdram - sdram - rtl + /EMS11_BB21Toplevel - rtl |home|amr|FPGA|TG68MiniSOC|Board|ems11-bb21|EMS11_BB21Toplevel.vhd/project - VirtualToplevel - rtl/myvga - vga_controller - rtl + /EMS11_BB30Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC.EMU|branches|burst8|Board|ems11-bb21|EMS11_BB30Toplevel.vhd/project - VirtualToplevel - rtl + /EMS11_BB30Toplevel - rtl D:|_home|emu|_User|Alastair-M-Robinson|GitHub|TG68_MiniSOC.git|branches|master|Board|ems11-bb37|EMS11_BB37Toplevel.vhd + /TG68KdotC_Kernel - logic |home|amr|FPGA|TG68MiniSOC|RTL|CPU|TG68KdotC_Kernel.vhd + + + EMS11_BB30Toplevel - rtl (D:/_home/emu/_User/Alastair-M-Robinson/GitHub/TG68_MiniSOC.git/branches/master/Board/ems11-bb37/EMS11_BB37Toplevel.vhd) + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000153000000020000000000000000000000000200000064ffffffff000000810000000300000002000001530000000100000003000000000000000100000003 + true + EMS11_BB30Toplevel - rtl (D:/_home/emu/_User/Alastair-M-Robinson/GitHub/TG68_MiniSOC.git/branches/master/Board/ems11-bb37/EMS11_BB37Toplevel.vhd) + + + + 1 + Design Utilities + Implement Design/Map + Implement Design/Map/Generate Post-Map Static Timing + Implement Design/Place & Route + Implement Design/Place & Route/Back-annotate Pin Locations + Implement Design/Place & Route/Generate IBIS Model + Implement Design/Place & Route/Generate Post-Place & Route Static Timing + Implement Design/Translate + User Constraints + + + Configure Target Device + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000 + false + Configure Target Device + + + + 1 + + + DualPortRAM.vhd + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000391000000040101000100000000000000000000000064ffffffff000000810000000000000004000000d200000001000000000000010900000001000000000000007900000001000000000000013d0000000100000000 + false + DualPortRAM.vhd + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000 + false + work + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000151000000010000000100000000000000000000000064ffffffff000000810000000000000001000001510000000100000000 + false + + + 000000ff0000000000000002000001380000011b01000000040100000002 + Implementation + + + 1 + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000186000000010000000100000000000000000000000064ffffffff000000810000000000000001000001860000000100000000 + false + + + + + 1 + User Constraints + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000186000000010000000100000000000000000000000064ffffffff000000810000000000000001000001860000000100000000 + false + + + + + + 1 + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000182000000010000000100000000000000000000000064ffffffff000000810000000000000001000001820000000100000000 + false + + + + + 2 + /EMS11_BB21Toplevel - rtl C:|Users|CHEMSTI|HOME|TG68_MiniSOC|branches|burst8|Board|ems11-bb21|EMS11_BB21Toplevel.vhd + /EMS11_BB30Toplevel - rtl |home|amr|FPGA|TG68MiniSOC|Board|ems11-bb30|EMS11_BB30Toplevel.vhd/project - VirtualToplevel - rtl + /abb_tb - behavior C:|Users|CHEMSTI|HOME|TG68_MiniSOC|branches|burst8|SOC|fpga|ems11-bb21|abb_tb.vhd/uut - EMS11_BB21Toplevel - rtl/project - VirtualToplevel - rtl/myaudio - sound_wrapper - rtl + /abb_tb - behavior C:|Users|CHEMSTI|HOME|TG68_MiniSOC|branches|burst8|SOC|fpga|ems11-bb21|abb_tb.vhd/uut - EMS11_BB21Toplevel - rtl/project - VirtualToplevel - rtl/myperipheral - peripheral_controller - rtl + /abb_tb - behavior C:|Users|CHEMSTI|HOME|TG68_MiniSOC|branches|burst8|SOC|fpga|ems11-bb21|abb_tb.vhd/uut - EMS11_BB21Toplevel - rtl/project - VirtualToplevel - rtl/myvga - vga_controller - rtl + + + EMS11_BB30Toplevel - rtl (/home/amr/FPGA/TG68MiniSOC/Board/ems11-bb30/EMS11_BB30Toplevel.vhd) + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001a7000000020000000000000000000000000200000064ffffffff000000810000000300000002000001a70000000100000003000000000000000100000003 + true + EMS11_BB30Toplevel - rtl (/home/amr/FPGA/TG68MiniSOC/Board/ems11-bb30/EMS11_BB30Toplevel.vhd) + + + + 1 + Design Utilities/Compile HDL Simulation Libraries + ISim Simulator + + + Design Utilities + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000182000000010000000100000000000000000000000064ffffffff000000810000000000000001000001820000000100000000 + false + Design Utilities + + + + 1 + + + Behavioral Check Syntax + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000182000000010000000100000000000000000000000064ffffffff000000810000000000000001000001820000000100000000 + false + Behavioral Check Syntax + + + + 1 + ISim Simulator + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000182000000010000000100000000000000000000000064ffffffff000000810000000000000001000001820000000100000000 + false + + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000151000000010000000100000000000000000000000064ffffffff000000810000000000000001000001510000000100000000 + false + + + + + 1 + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000151000000010000000100000000000000000000000064ffffffff000000810000000000000001000001510000000100000000 + false + + + + + 1 + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000182000000010000000100000000000000000000000064ffffffff000000810000000000000001000001820000000100000000 + false + + + + + 1 + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000182000000010000000100000000000000000000000064ffffffff000000810000000000000001000001820000000100000000 + false + + + diff --git a/SOC/fpga/ems11-bb37/pepExtractor.prj b/SOC/fpga/ems11-bb37/pepExtractor.prj new file mode 100644 index 0000000..0761429 --- /dev/null +++ b/SOC/fpga/ems11-bb37/pepExtractor.prj @@ -0,0 +1 @@ +work "C:/Users/CHEMSTI/HOME/TG68_MiniSOC/branches/burst8/Board/ems11-bb21/EMS11_BB21Toplevel.vhd" diff --git a/SOC/fpga/ems11-bb37/webtalk_impact.xml b/SOC/fpga/ems11-bb37/webtalk_impact.xml new file mode 100644 index 0000000..ae3889c --- /dev/null +++ b/SOC/fpga/ems11-bb37/webtalk_impact.xml @@ -0,0 +1,39 @@ + + + + +
+ + +
+
+ + + + +
+
+ + + + + + + + + + + + + + + + + + +
+ +